s3demo.npl

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

JDF G
// Created by Project Navigator ver 1.0
PROJECT S3Demo
DESIGN s3demo
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s400
DEVICETIME 1145510337
DEVPKG ft256
DEVPKGTIME 1089651388
DEVSPEED -5
DEVSPEEDTIME 1089651388
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE vga_main.vhd
SOURCE kb2vhdl.vhd
SOURCE S3demo.vhd
DEPASSOC s3demo S3demo.ucf
[Normal]
xilxBitgStart_Clk=xstvhd, spartan3, VHDL.t_bitFile, 1145510733, CCLK
[STRATEGY-LIST]
Normal=True