s3demo.twr

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

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Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

E:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml s3demo s3demo.ncd -o
s3demo.twr s3demo.pcf


Design file:              s3demo.ncd
Physical constraint file: s3demo.pcf
Device,speed:             xc3s400,-5 (ADVANCED 1.32 2004-06-25)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock mclk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
an<0>       |   10.774(R)|mclk_BUFGP        |   0.000|
an<1>       |   10.522(R)|mclk_BUFGP        |   0.000|
ssg<0>      |   11.981(R)|mclk_BUFGP        |   0.000|
ssg<1>      |   11.845(R)|mclk_BUFGP        |   0.000|
ssg<2>      |   11.431(R)|mclk_BUFGP        |   0.000|
ssg<3>      |   11.916(R)|mclk_BUFGP        |   0.000|
ssg<4>      |   11.779(R)|mclk_BUFGP        |   0.000|
ssg<5>      |   12.289(R)|mclk_BUFGP        |   0.000|
ssg<6>      |   11.814(R)|mclk_BUFGP        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock mclk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
mclk           |    4.536|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
btn<0>         |an<0>          |    9.208|
btn<0>         |ssg<7>         |    6.185|
btn<1>         |an<1>          |    9.191|
btn<2>         |an<2>          |    8.388|
btn<3>         |an<3>          |    9.111|
swt<0>         |an<0>          |    8.991|
swt<0>         |an<1>          |    8.752|
swt<0>         |an<2>          |    8.612|
swt<0>         |an<3>          |    9.572|
swt<0>         |led<0>         |    6.999|
swt<0>         |ssg<0>         |   10.435|
swt<0>         |ssg<1>         |    8.786|
swt<0>         |ssg<2>         |    9.823|
swt<0>         |ssg<3>         |    9.160|
swt<0>         |ssg<4>         |   10.171|
swt<0>         |ssg<5>         |   10.392|
swt<0>         |ssg<6>         |    9.058|
swt<1>         |led<1>         |    7.664|
swt<2>         |led<2>         |    6.874|
swt<3>         |led<3>         |    6.678|
swt<4>         |led<4>         |    7.353|
swt<5>         |led<5>         |    7.454|
swt<6>         |led<6>         |    7.355|
swt<7>         |led<7>         |    7.665|
---------------+---------------+---------+

Analysis completed Thu Apr 20 13:19:27 2006
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Peak Memory Usage: 59 MB