s3demo.par

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

BAYI::  Thu Apr 20 13:19:22 2006


E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 s3demo_map.ncd
s3demo.ncd s3demo.pcf 


Constraints file: s3demo.pcf

Loading device database for application Par from file "s3demo_map.ncd".
   "s3demo" is an NCD, version 2.38, device xc3s400, package ft256, speed -5
Loading device for application Par from file '3s400.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolved that IOB <an<0>> must be placed at site E13.
Resolved that IOB <an<1>> must be placed at site F14.
Resolved that IOB <an<2>> must be placed at site G14.
Resolved that IOB <an<3>> must be placed at site D14.
Resolved that IOB <btn<0>> must be placed at site M13.
Resolved that IOB <led<0>> must be placed at site K12.
Resolved that IOB <btn<1>> must be placed at site M14.
Resolved that IOB <kc> must be placed at site M16.
Resolved that IOB <led<1>> must be placed at site P14.
Resolved that IOB <kd> must be placed at site M15.
Resolved that IOB <btn<2>> must be placed at site L13.
Resolved that IOB <led<2>> must be placed at site L12.
Resolved that IOB <btn<3>> must be placed at site L14.
Resolved that IOB <led<3>> must be placed at site N14.
Resolved that IOB <led<4>> must be placed at site P13.
Resolved that IOB <led<5>> must be placed at site N12.
Resolved that IOB <blu> must be placed at site R11.
Resolved that IOB <led<6>> must be placed at site P12.
Resolved that IOB <hs> must be placed at site R9.
Resolved that IOB <led<7>> must be placed at site P11.
Resolved that IOB <swt<0>> must be placed at site F12.
Resolved that IOB <grn> must be placed at site T12.
Resolved that IOB <swt<1>> must be placed at site G12.
Resolved that IOB <swt<2>> must be placed at site H14.
Resolved that IOB <vs> must be placed at site T10.
Resolved that IOB <swt<3>> must be placed at site H13.
Resolved that IOB <swt<4>> must be placed at site J14.
Resolved that IOB <red> must be placed at site R12.
Resolved that IOB <swt<5>> must be placed at site J13.
Resolved that IOB <swt<6>> must be placed at site K14.
Resolved that IOB <swt<7>> must be placed at site K13.
Resolved that IOB <ssg<0>> must be placed at site E14.
Resolved that IOB <mclk> must be placed at site T9.
Resolved that IOB <ssg<1>> must be placed at site G13.
Resolved that IOB <ssg<2>> must be placed at site N15.
Resolved that IOB <ssg<3>> must be placed at site P15.
Resolved that IOB <ssg<4>> must be placed at site R16.
Resolved that IOB <ssg<5>> must be placed at site F13.
Resolved that IOB <ssg<6>> must be placed at site N16.
Resolved that IOB <ssg<7>> must be placed at site P16.


Device utilization summary:

   Number of External IOBs            40 out of 173    23%
      Number of LOCed External IOBs   40 out of 40    100%

   Number of Slices                   75 out of 3584    2%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9898a1) REAL time: 2 secs 

.
Phase 3.8
..
Phase 3.8 (Checksum:99404d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file s3demo.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 429 unrouted;       REAL time: 2 secs 

Phase 2: 380 unrouted;       REAL time: 3 secs 

Phase 3: 112 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|        mclk_BUFGP       |  BUFGMUX0| No   |   20 |  0.017     |  0.901      |
+-------------------------+----------+------+------+------------+-------------+
|     kb1_clkDiv<3>       |   Local  |      |    5 |  0.627     |  1.668      |
+-------------------------+----------+------+------+------------+-------------+
|        clkdiv<23>       |   Local  |      |    3 |  0.000     |  1.389      |
+-------------------------+----------+------+------+------------+-------------+
|       vga1_clkdiv       |   Local  |      |   12 |  0.622     |  2.015      |
+-------------------------+----------+------+------+------------+-------------+
|           kb1_KCI       |   Local  |      |   15 |  0.027     |  1.785      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 113


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.778
   The MAXIMUM PIN DELAY IS:                               2.683
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.769

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         320         101           8           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  68 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file s3demo.ncd.


PAR done.