_pace.ucf

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "ssg<7>"  LOC = "P16"  ;
NET "swt<0>"  LOC = "F12"  ;
NET "swt<1>"  LOC = "G12"  ;
NET "swt<2>"  LOC = "H14"  ;
NET "swt<3>"  LOC = "H13"  ;
NET "swt<4>"  LOC = "J14"  ;
NET "swt<5>"  LOC = "J13"  ;
NET "swt<6>"  LOC = "K14"  ;
NET "swt<7>"  LOC = "K13"  ;
NET "vs"  LOC = "T10"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE