hdpdeps.ref

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

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FL C:/Xilinx-Projects/Working/S3Demo/vga_main.vhd 2004/07/06.10:03:11
FL G:/资料/Spartan-3/S3Demo/vga_main.vhd 2004/07/06.10:03:12
EN work/VGACONTROLLER   FL G:/资料/Spartan-3/S3Demo/vga_main.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/VGACONTROLLER/BEHAVIORAL FL G:/资料/Spartan-3/S3Demo/vga_main.vhd \
      EN work/VGACONTROLLER
FL G:/资料/Spartan-3/S3Demo/S3demo.vhd 2004/07/12.10:30:16
EN work/S3DEMO          FL G:/资料/Spartan-3/S3Demo/S3demo.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/S3DEMO/BEHAVIORAL FL G:/资料/Spartan-3/S3Demo/S3demo.vhd EN work/S3DEMO \
      CP VGACONTROLLER  CP KEYBOARDVHDL
FL C:/Xilinx-Projects/Working/S3Demo/S3demo.vhd 2004/07/12.10:30:14
FL C:/Xilinx-Projects/Working/S3Demo/kb2vhdl.vhd 2004/07/07.10:59:57
FL G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd 2004/07/07.10:59:58
EN work/KEYBOARDVHDL    FL G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/KEYBOARDVHDL/BEHAVIORAL FL G:/资料/Spartan-3/S3Demo/kb2vhdl.vhd \
      EN work/KEYBOARDVHDL