📄 s3demo.mrp
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Release 6.3i Map G.35Xilinx Mapping Report File for Design 's3demo'Design Information------------------Command Line : E:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-ft256-5 -cm
area -pr b -k 4 -c 100 -tx off -o s3demo_map.ncd s3demo.ngd s3demo.pcf Target Device : x3s400Target Package : ft256Target Speed : -5Mapper Version : spartan3 -- $Revision: 1.16.8.2 $Mapped Date : Thu Apr 20 13:19:20 2006Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 94 out of 7,168 1% Number of 4 input LUTs: 54 out of 7,168 1%Logic Distribution: Number of occupied Slices: 75 out of 3,584 2% Number of Slices containing only related logic: 75 out of 75 100% Number of Slices containing unrelated logic: 0 out of 75 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 107 out of 7,168 1% Number used as logic: 54 Number used as a route-thru: 53 Number of bonded IOBs: 40 out of 173 23% IOB Flip Flops: 2 Number of GCLKs: 1 out of 8 12%Total equivalent gate count for design: 1,434Additional JTAG gate count for IOBs: 1,920Peak Memory Usage: 74 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "mclk_BUFGP" (output signal=mclk_BUFGP)Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| an<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || an<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || an<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || an<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || blu | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || btn<0> | IOB | INPUT | LVCMOS25 | | | | | || btn<1> | IOB | INPUT | LVCMOS25 | | | | | || btn<2> | IOB | INPUT | LVCMOS25 | | | | | || btn<3> | IOB | INPUT | LVCMOS25 | | | | | || grn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || hs | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || kc | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || kd | IOB | INPUT | LVCMOS25 | | | INFF1 | | IFD || led<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || led<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || mclk | IOB | INPUT | LVCMOS25 | | | | | || red | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ssg<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || swt<0> | IOB | INPUT | LVCMOS25 | | | | | || swt<1> | IOB | INPUT | LVCMOS25 | | | | | || swt<2> | IOB | INPUT | LVCMOS25 | | | | | || swt<3> | IOB | INPUT | LVCMOS25 | | | | | || swt<4> | IOB | INPUT | LVCMOS25 | | | | | || swt<5> | IOB | INPUT | LVCMOS25 | | | | | || swt<6> | IOB | INPUT | LVCMOS25 | | | | | || swt<7> | IOB | INPUT | LVCMOS25 | | | | | || vs | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 40Number of Equivalent Gates for Design = 1,434Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 0GCLKs = 1ICAPs = 018X18 Multipliers = 0Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 87IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 2IOB Flip Flops = 2Unbonded IOBs = 0Bonded IOBs = 40Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFXs = 7MULTANDs = 04 input LUTs used as Route-Thrus = 534 input LUTs = 54Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 85Slice Flip Flops = 94SliceMs = 0SliceLs = 75Slices = 75Number of LUT signals with 4 loads = 1Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 6Number of LUT signals with 1 load = 40NGM Average fanout of LUT = 2.07NGM Maximum fanout of LUT = 10NGM Average fanin for LUT = 3.4259Number of LUT symbols = 54Number of IPAD symbols = 15Number of IBUF symbols = 15⌨️ 快捷键说明
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