booth.cr.mti

the booth algorithm to implement the 32bits multiplication.

D:/HDLDesign/Lab0/fulladder32.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab0/fulladder32.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fulladder32
-- Compiling architecture circuits of fulladder32

} {} {}} D:/HDLDesign/Lab2/QRegister.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/QRegister.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity qregister
-- Compiling architecture behav of qregister

} {} {}} D:/HDLDesign/Lab2/ARegister.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/ARegister.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity aregister
-- Compiling architecture behav of aregister

} {} {}} D:/HDLDesign/Lab2/mul32c.vhd {0 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/mul32c.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity add32csa
-- Compiling architecture circuits of add32csa
-- Compiling entity mul32c
-- Compiling architecture circuits of mul32c
** Error: D:/HDLDesign/Lab2/mul32c.vhd(82): near "The": syntax error

} {9.0 10.0} {}} D:/HDLDesign/Lab2/mul_ser.vhd {0 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/mul_ser.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity mul_ser
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package textio
-- Loading package std_logic_textio
-- Compiling architecture schematic of mul_ser
** Error: (vcom-11) Could not find work.add32.
** Error: D:/HDLDesign/Lab2/mul_ser.vhd(39): Cannot find expanded name: work.add32.
** Error: D:/HDLDesign/Lab2/mul_ser.vhd(39): Unknown record element "add32".
** Error: D:/HDLDesign/Lab2/mul_ser.vhd(66): VHDL Compiler exiting

} {10.0 14.0} {}} D:/HDLDesign/Lab0/fulladder.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab0/fulladder.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity fulladder
-- Compiling architecture structural of fulladder

} {} {}} D:/HDLDesign/Lab2/DRegister.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/DRegister.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity dregister
-- Compiling architecture behav of dregister

} {} {}} D:/HDLDesign/Lab2/bmul_ser.vhd {1 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/bmul_ser.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Compiling entity bmul_ser
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package textio
-- Loading package std_logic_textio
-- Compiling architecture schematic of bmul_ser

} {} {}} D:/HDLDesign/Lab2/mul32c_test.vhd {0 {vcom -work work -2002 -explicit D:/HDLDesign/Lab2/mul32c_test.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package textio
-- Loading package std_logic_1164
-- Loading package std_logic_textio
-- Loading package std_logic_arith
-- Compiling entity mul32c_test
-- Compiling architecture circuits of mul32c_test
-- Compiling configuration mul32c_config
-- Loading entity mul32c_test
-- Loading architecture circuits of mul32c_test
** Error: (vcom-11) Could not find work.mul32c.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(98): Cannot find expanded name: work.mul32c.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(98): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(100): Components must be fully bound.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(101): 'stage' must be a label on a block or generate statement.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(102): (vcom-1141) 'add32csa' is not a component declaration
** Error: (vcom-11) Could not find work.add32csa.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(102): Cannot find expanded name: work.add32csa.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(102): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(104): Components must be fully bound.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(105): 'stage' must be a label on a block or generate statement.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(106): (vcom-1141) 'fadd' is not a component declaration
** Error: (vcom-11) Could not find work.fadd.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(106): Cannot find expanded name: work.fadd.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(106): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(113): (vcom-1141) 'add32csa' is not a component declaration
** Error: (vcom-11) Could not find work.add32csa.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(113): Cannot find expanded name: work.add32csa.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(113): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(115): Components must be fully bound.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(116): 'stage' must be a label on a block or generate statement.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(117): (vcom-1141) 'fadd' is not a component declaration
** Error: (vcom-11) Could not find work.fadd.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(117): Cannot find expanded name: work.fadd.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(117): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(123): (vcom-1141) 'add32' is not a component declaration
** Error: (vcom-11) Could not find work.add32.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(123): Cannot find expanded name: work.add32.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(123): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(125): Components must be fully bound.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(126): (vcom-1141) 'add4' is not a component declaration
** Error: (vcom-11) Could not find work.add4.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(126): Cannot find expanded name: work.add4.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(126): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(128): Components must be fully bound.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(129): (vcom-1141) 'fadd' is not a component declaration
** Error: (vcom-11) Could not find work.fadd.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(129): Cannot find expanded name: work.fadd.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(129): (vcom-1105) 'work' is not an entity.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(136): Component all: mul32c does not have a primary binding.
** Error: D:/HDLDesign/Lab2/mul32c_test.vhd(138): VHDL Compiler exiting

} {13.0 54.0} {}}