_info

the booth algorithm to implement the 32bits multiplication.

m255
13
cModel Technology
dD:\HDLDesign\Lab0
Eadd32csa
w1150680963
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/mul32c.vhd
l0
L8
V6D]L0:o1Dz8:<Zkz;49n83
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Acircuits
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work add32csa 6D]L0:o1Dz8:<Zkz;49n83
l28
L18
VaJ8>Li^KfE[Rz[BZ23KCa1
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Earegister
w1150679249
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/ARegister.vhd
l0
L4
V1WLTDh3>1TA:0iLW302O;0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehav
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work aregister 1WLTDh3>1TA:0iLW302O;0
l14
L12
VcNKZDdVZ9NPmIS0fJ4KbO1
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Ebmul_ser
w1151111085
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/bmul_ser.vhd
l0
L19
VGIbaP;eUioADzZj=GR]Z>2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Aschematic
DE work bmul_ser GIbaP;eUioADzZj=GR]Z>2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
l63
L28
V]XzGJAK9z;Z=V8FO6YENG0
OE;C;6.0;29
32
M4 ieee std_logic_1164
M3 ieee std_logic_arith
M2 ieee std_logic_textio
M1 std textio
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Edregister
w1150678505
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/DRegister.vhd
l0
L4
V:]US@n0]YL<2a1DYM?J5V3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehav
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work dregister :]US@n0]YL<2a1DYM?J5V3
l14
L12
VE[Bk_kW=iem@RDkGl@;h]3
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Efulladder
w1150569799
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab0/fulladder.vhd
l0
L7
VJ6aY]A=C1X7<ZF`Lc]@?B3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Astructural
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work fulladder J6aY]A=C1X7<ZF`Lc]@?B3
l36
L19
VdkH=gN3LM?gW9[HMoH1Ti2
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Efulladder32
w1150570355
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab0/fulladder32.vhd
l0
L3
ViYX8EXfI9hRK9G_I]^]Ql2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Acircuits
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work fulladder32 iYX8EXfI9hRK9G_I]^]Ql2
l19
L11
V5S8:R77aV;K[RIoOe6_`U0
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Emul32c
w1150680963
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/mul32c.vhd
l0
L39
VhO=6D>f2^bXzDTBeoAlNH1
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Acircuits
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work mul32c hO=6D>f2^bXzDTBeoAlNH1
l68
L45
VcQRGkPf?6daE^i?`6UQN[0
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Emul32c_test
w1150681004
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/mul32c_test.vhd
l0
L14
VA=]AOIT[W<gdNc8?Y<D>^0
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Acircuits
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DE work mul32c_test A=]AOIT[W<gdNc8?Y<D>^0
l49
L17
V_FP5d[A;j5`Td`[FZ=f2c3
OE;C;6.0;29
32
M4 std textio
M3 ieee std_logic_1164
M2 ieee std_logic_textio
M1 ieee std_logic_arith
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Emul_ser
w1150680793
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/mul_ser.vhd
l0
L6
VU_hQ72GnJ2Zb2PTd0mgID2
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Eqregister
w1150680422
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dD:\HDLDesign\Lab2
FD:/HDLDesign/Lab2/QRegister.vhd
l0
L4
V@IV]:mUj_nBG:SW36XoSI3
OE;C;6.0;29
32
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000
Abehav
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work qregister @IV]:mUj_nBG:SW36XoSI3
l19
L14
VikDAc^Y`MYPK9coVZDKTi2
OE;C;6.0;29
32
M1 ieee std_logic_1164
o-work work -2002 -explicit
tExplicit 1GenerateLoopIterationMax 100000