writer_fsm1.vhd

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools

--LIBRARY top_level_lib;
LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY writer_fsm IS
PORT(
	wclk: IN std_logic;
	rstb: IN std_logic;

	isop: IN std_logic;
	ieop: IN std_logic;
	ivalid: IN std_logic;
	iready: OUT std_logic;

	wp_load: OUT std_logic;
	wp_enb: OUT std_logic;

	wr_done: OUT std_logic;
	fullemptyb: IN std_logic;

	wport_meb: OUT std_logic;
	wport_web: OUT std_logic;
	wport_reb: OUT std_logic;
	wport_din_eop: OUT std_logic
);
END writer_fsm;

ARCHITECTURE behav OF writer_fsm IS
TYPE state_list IS (RESET, IDLE, SOP, EOP, DATA, NODATA, ONEBYTE);

SIGNAL state, next_state: state_list;
SIGNAL isop_s, ieop_s, ivalid_s, ieop_s2, ieop_s3: std_logic;
SIGNAL onebyte_i: std_logic;
SIGNAL pkt_start_i, pkt_end_i : std_logic;
SIGNAL wp_enb_i : std_logic;

BEGIN
wp_enb <= wp_enb_i;

wport_meb <= NOT(wp_enb_i);
wport_web <= NOT(wp_enb_i);
wport_reb <= '1';

wport_din_eop <= ieop_s3;

--get input
mornitor_input: PROCESS(rstb, wclk)
BEGIN
    IF (rstb /= '1') THEN
        isop_s <= '0';
        ieop_s <= '0';
        ieop_s2 <= '0';
        ieop_s3 <= '0';
        ivalid_s <= '0';
    ELSIF (wclk'EVENT AND wclk = '1') THEN
        isop_s <= isop;
        ieop_s <= ieop;
        ieop_s2 <= ieop_s;
        ieop_s3 <= ieop_s2;
        ivalid_s <= ivalid;
    END IF;
END PROCESS mornitor_input;

onebyte_i <= ivalid_s AND isop_s AND ieop_s;
pkt_start_i <= ivalid_s AND isop_s AND NOT(ieop_s);
pkt_end_i <= ivalid_s AND NOT(isop_s) AND ieop_s;

decode: PROCESS(state, ivalid_s, onebyte_i, pkt_start_i, pkt_end_i)
BEGIN
    CASE state IS
        WHEN RESET =>
            next_state <= IDLE;
        WHEN IDLE =>
            IF (onebyte_i = '1') THEN
                next_state <= ONEBYTE;
            ELSIF (pkt_start_i = '1') THEN
                next_state <= SOP;
            ELSE
                next_state <= IDLE;
            END IF;
        WHEN SOP =>
            IF (onebyte_i = '1') THEN
                next_state <= ONEBYTE;
            ELSIF (pkt_start_i = '1') THEN
                next_state <= SOP;
            ELSIF (pkt_end_i = '1') THEN
                next_state <= EOP;
            ELSIF (ivalid_s = '1') THEN
                next_state <= DATA;
            ELSE
                next_state <= NODATA;
            END IF;
        WHEN DATA =>
            IF (onebyte_i = '1') THEN
                next_state <= ONEBYTE;
            ELSIF (pkt_start_i = '1') THEN
                next_state <= SOP;
            ELSIF (pkt_end_i = '1') THEN
                next_state <= EOP;
            ELSIF (ivalid_s = '1') THEN
                next_state <= DATA;
            ELSE
                next_state <= NODATA;
            END IF;
        WHEN EOP =>
            next_state <= IDLE;
        WHEN NODATA =>
            IF (onebyte_i = '1') THEN
                next_state <= ONEBYTE;
            ELSIF (pkt_start_i = '1') THEN
                next_state <= SOP;
            ELSIF (pkt_end_i = '1') THEN
                next_state <= EOP;
            ELSIF (ivalid_s = '1') THEN
                next_state <= DATA;
            ELSE
                next_state <= NODATA;
            END IF;
        WHEN ONEBYTE =>
            next_state <= IDLE;
        WHEN OTHERS =>
            next_state <= IDLE;
    END CASE;
END PROCESS decode;
    
state_change: PROCESS(rstb, wclk)
BEGIN
    IF (rstb /= '1') THEN
        state <= RESET;
    ELSIF (wclk'EVENT AND wclk = '1') THEN
        state <= next_state;
    END IF;
END PROCESS state_change;

cmblogic: PROCESS(state, next_state, fullemptyb)
BEGIN
    IF (state = SOP OR state = ONEBYTE) THEN
        wp_load <= '1';
    ELSE
        wp_load <= '0';
    END IF;
    
    IF (next_state = EOP OR next_state = ONEBYTE) THEN
        wr_done <= '1';
    ELSE
        wr_done <= '0';
    END IF;
    
    iready <= NOT(fullemptyb);
END PROCESS cmblogic;

seqlogic: PROCESS(rstb, wclk)
BEGIN
    IF (rstb /= '1') THEN
        wp_enb_i <= '0';
    ELSIF (wclk'EVENT AND wclk = '1') THEN
        IF (state = SOP OR state = EOP OR state = DATA OR state = ONEBYTE) THEN
            wp_enb_i <= '1';
        ELSE
            wp_enb_i <= '0';
        END IF;
    END IF;
END PROCESS seqlogic;

END ARCHITECTURE behav;