reader_fsm.vhd

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools

--LIBRARY top_level_lib;
LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY reader_fsm IS
PORT(
	rclk: IN std_logic;
	rstb: IN std_logic;

	fullemptyb_sync_pulse: IN std_logic;
	rport_dout_eop: IN std_logic;
	
	osop: OUT std_logic;
	oeop: OUT std_logic;
	ovalid: OUT std_logic;

	rp_load: OUT std_logic;
	rp_enb: OUT std_logic;
	rd_done: OUT std_logic;

	rport_meb: OUT std_logic;
	rport_web: OUT std_logic;
	rport_reb: OUT std_logic
);
END reader_fsm;

ARCHITECTURE behav OF reader_fsm IS
TYPE state_list IS (RESET, IDLE, SOP, EOP, DATA);

SIGNAL currentState, nextState: state_list;
SIGNAL rpenbvalue, ovalidvalue: std_logic;
SIGNAL osopreg1, osopreg2: std_logic;
SIGNAL dataflag: std_logic;

BEGIN
rp_enb <= rpenbvalue;
rport_reb <= '0';
rport_web <= '1';

statedecode: PROCESS(currentState, fullemptyb_sync_pulse, rport_dout_eop)
BEGIN
    CASE currentState IS
        WHEN RESET =>
            nextState <= IDLE;
            
        WHEN IDLE =>
            IF (fullemptyb_sync_pulse = '1') THEN
                nextState <= SOP;
            ELSE
                nextState <= IDLE;
            END IF;
        
        WHEN SOP =>
            nextState <= DATA;
            
        WHEN DATA =>
            IF (rport_dout_eop = '1' AND ovalidvalue = '1') THEN
                nextState <= EOP;
            ELSE
                nextState <= DATA;
            END IF;
            
        WHEN EOP =>
            nextState <= IDLE;
            
        WHEN OTHERS =>
            nextState <= IDLE;
    END CASE;
END PROCESS statedecode;

cmblogic: PROCESS(currentState, nextState, fullemptyb_sync_pulse, dataflag)
BEGIN
    IF (currentState = RESET OR currentState = IDLE OR currentState = SOP) THEN 
       rp_load <= '1';
    ELSE
       rp_load <= '0';
    END IF;
    
    IF (nextState = DATA AND currentState = DATA) THEN
        rpenbvalue <= '1';
    ELSE
        rpenbvalue <= '0';
    END IF;
    
    IF (dataflag = '1' AND currentState = DATA) THEN
        ovalidvalue <= '1';
    ELSE
        ovalidvalue <= '0';
    END IF;
END PROCESS cmblogic;

seqlogic: PROCESS(rstb, rclk)
BEGIN
    IF (rstb /= '1') THEN
        osopreg1 <= '0';
        osopreg2 <= '0';
        osop <= '0';
        oeop <= '0';
        rd_done <= '0';
        dataflag <= '0';
        ovalid <= '0';
        rport_meb <= '0';

        currentState <= RESET;

    ELSIF (rclk'EVENT AND rclk = '1') THEN
        IF (currentState = SOP) THEN
            osopreg1 <= '1';
        ELSE
            osopreg1 <= '0';
        END IF;
        
        osopreg2 <= osopreg1;
        osop <= osopreg2;
        
        IF (nextState = EOP) THEN
            oeop <= '1';
            rd_done <= '1';
        ELSE
            oeop <= '0';
            rd_done <= '0';
        END IF;
        
        IF (currentState = DATA) THEN
            dataflag <= '1';
        ELSE
            dataflag <= '0';
        END IF;
        
        ovalid <= ovalidvalue;
        
        IF (nextState = DATA) THEN
            rport_meb <= '1';
        ELSE
            rport_meb <= '0';
        END IF;

        currentState <= nextState;

    END IF;
        
END PROCESS seqlogic;

END behav;