writer_fsm.vhd

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools

--This writer fsm will control the writer operation

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY writer_fsm IS
PORT(
	wclk: IN std_logic;
	rstb: IN std_logic;

	isop: IN std_logic;
	ieop: IN std_logic;
	ivalid: IN std_logic;

	fullemptyb: IN std_logic;

	wp_load: OUT std_logic;
	wp_enb: OUT std_logic;

	iready: OUT std_logic;
	wr_done: OUT std_logic;

	wport_meb: OUT std_logic;
	wport_web: OUT std_logic;
	wport_reb: OUT std_logic
);
END writer_fsm;

ARCHITECTURE behav OF writer_fsm IS
TYPE slist IS (RESET, IDLE, ONEBYTE, SOP, EOP, DATA, NODATA);
SIGNAL currentState, nextState: slist;
SIGNAL isopvalue, ieopvalue, ivalidvalue: std_logic;

BEGIN
fsmlogic: PROCESS(currentState, isopvalue, ieopvalue, ivalidvalue)
BEGIN
    CASE currentState IS
        WHEN RESET =>
            nextState <= IDLE;
        WHEN IDLE =>
            IF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '1') THEN
                nextState <= ONEBYTE;
            ELSIF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '0') THEN
                nextState <= SOP;
            ELSE
                nextState <= IDLE;
            END IF;
        WHEN ONEBYTE =>
            nextState <= IDLE;
        WHEN SOP =>
            IF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '1') THEN
                nextState <= ONEBYTE;
            ELSIF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '0') THEN
                nextState <= SOP;
            ELSIF (ivalidvalue = '1' AND isopvalue = '0' AND ieopvalue = '1') THEN
                nextState <= EOP;
            ELSIF (ivalidvalue = '1') THEN
                nextState <= DATA;
            ELSE
                nextState <= NODATA;
            END IF;
        WHEN EOP =>
            nextState <= IDLE;
        WHEN DATA =>
            IF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '1') THEN
                nextState <= ONEBYTE;
            ELSIF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '0') THEN
                nextState <= SOP;
            ELSIF (ivalidvalue = '1' AND isopvalue = '0' AND ieopvalue = '1') THEN
                nextState <= EOP;
            ELSIF (ivalidvalue = '1') THEN
                nextState <= DATA;
            ELSE
                nextState <= NODATA;
            END IF;
        WHEN NODATA =>
            IF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '1') THEN
                nextState <= ONEBYTE;
            ELSIF (ivalidvalue = '1' AND isopvalue = '1' AND ieopvalue = '0') THEN
                nextState <= SOP;
            ELSIF (ivalidvalue = '1' AND isopvalue = '0' AND ieopvalue = '1') THEN
                nextState <= EOP;
            ELSIF (ivalidvalue = '1') THEN
                nextState <= DATA;
            ELSE
                nextState <= NODATA;
            END IF;
        WHEN OTHERS =>
            nextState <= IDLE;
    END CASE;
END PROCESS fsmlogic;
    
cmblogic: PROCESS(currentState, nextState, fullemptyb)
BEGIN
    IF (currentState = SOP OR currentState = ONEBYTE) THEN
        wp_load <= '1';
    ELSE
        wp_load <= '0';
    END IF;
    
    IF (nextState = EOP OR nextState = ONEBYTE) THEN
        wr_done <= '1';
    ELSE
        wr_done <= '0';
    END IF;
    
    iready <= NOT(fullemptyb);
END PROCESS cmblogic;

seqlogic: PROCESS(rstb, wclk)
BEGIN
    IF (rstb /= '1') THEN
        isopvalue <= '0';
        ieopvalue <= '0';
        ivalidvalue <= '0';

        wp_enb <= '0';
        wport_meb <= '1';
        wport_web <= '1';

        currentState <= RESET;
    ELSIF (wclk'EVENT AND wclk = '1') THEN
        isopvalue <= isop;
        ieopvalue <= ieop;
        ivalidvalue <= ivalid;

        IF (currentState = SOP OR currentState = EOP OR currentState = DATA OR currentState = ONEBYTE) THEN
            wp_enb <= '1';
            wport_meb <= '0';
            wport_web <= '0';
        ELSE
            wp_enb <= '0';
            wport_meb <= '1';
            wport_web <= '1';
        END IF;

        currentState <= nextState;
    END IF;
END PROCESS seqlogic;

wport_reb <= '1';

END ARCHITECTURE behav;