📄 synchronizer.vhd.bak
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--LIBRARY top_level_lib;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY synchronizer ISPORT( wclk: IN std_logic; rclk: IN std_logic; rstb: IN std_logic; wr_done: IN std_logic; rd_done: IN std_logic; fullemptyb: OUT std_logic; fullemptyb_sync_pulse: OUT std_logic);END synchronizer;ARCHITECTURE behav OF synchronizer ISSIGNAL fullemptybvalue: std_logic;SIGNAL fullemptybsync1, fullemptybsync2, fullemptybsync3: std_logic;SIGNAL rdevent: std_logic;SIGNAL rdsync1, rdsync2: std_logic;SIGNAL rdrsbt: std_logic;BEGIN-- synchronize the rd_done input to wclkrdrsbt <= rstb AND NOT(rdsync2);rd_done_event: PROCESS (rdrsbt, rclk)BEGINIF (rdrsbt /= '1') THEN rdevent <= '0';ELSIF (rclk'EVENT AND rclk = '1') THEN IF (rd_done = '1') THEN rdevent <= '1'; ELSE rdevent <= rdevent; END IF;END IF;END PROCESS rd_done_event;rd_done_sync: PROCESS (rstb, wclk)BEGINIF (rstb /= '1') THEN rdsync1 <= '0'; rdsync2 <= '0';ELSIF (wclk'EVENT AND wclk = '1') THEN IF (rdsync2 = '1') THEN rdsync1 <= '0'; rdsync2 <= '0'; ELSE rdsync1 <= rdevent; rdsync2 <= rdsync1; END IF;END IF;END PROCESS rd_done_sync;-- generate the full/empty signalfullemptyb <= fullemptybvalue;fullemptyb_generate: PROCESS(rstb, wclk)BEGINIF (rstb /= '1') THEN fullemptybvalue <= '0';ELSIF (wclk'EVENT AND wclk = '1') THEN IF (wr_done = '1') THEN fullemptybvalue <= '1'; ELSIF (rdsync2 = '1') THEN fullemptybvalue <= '0'; ELSE fullemptybvalue <= fullemptybvalue; END IF;END IF;END PROCESS fullemptyb_generate;-- synchronize the empty signal to rclkfullemptyb_sync: PROCESS(rstb, rclk)BEGINIF (rstb /= '1') THEN fullemptybsync1 <= '0'; fullemptybsync2 <= '0'; fullemptybsync3 <= '0';ELSIF (rclk'EVENT AND rclk = '1') THEN fullemptybsync1 <= fullemptybvalue; fullemptybsync2 <= fullemptybsync1; fullemptybsync3 <= fullemptybsync2;END IF;END PROCESS fullemptyb_sync; fullemptyb_sync_pulse <= fullemptybsync2 AND NOT(fullemptybsync3);END behav;
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