fsm_tb.vhd

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
--use work.all;

ENTITY fsm_tb IS
END fsm_tb;

ARCHITECTURE behavial of fsm_tb IS
COMPONENT writer_fsm 
port(		
	wclk: IN std_logic;
	rstb: IN std_logic;

	isop: IN std_logic;
	ieop: IN std_logic;
	ivalid: IN std_logic;
	fullemptyb: IN std_logic;

	wp_load: OUT std_logic;
	wp_enb: OUT std_logic;

	iready: OUT std_logic;
	wr_done: OUT std_logic;

	wport_meb: OUT std_logic;
	wport_web: OUT std_logic;
	wport_reb: OUT std_logic
);
END COMPONENT;


COMPONENT reader_fsm 
port(		
	rclk: IN std_logic;
	rstb: IN std_logic;

	fullemptyb_sync_pulse: IN std_logic;
	rport_dout_eop: IN std_logic;
	
	osop: OUT std_logic;
	oeop: OUT std_logic;
	ovalid: OUT std_logic;

	rp_load: OUT std_logic;
	rp_enb: OUT std_logic;
	rd_done: OUT std_logic;

	rport_meb: OUT std_logic;
	rport_web: OUT std_logic;
	rport_reb: OUT std_logic
);
END COMPONENT;

signal s0, s1, s2, s3, sclk : std_logic := '0';
signal feb : std_logic := '0';
signal pointerload, pointerenb : std_logic := '0';
signal ready, readerdone: std_logic := '0';
signal portmeb, portweb, portreb : std_logic := '0';
BEGIN

--Test RFSM
RFSM: reader_fsm port map(
   rclk => sclk, rstb => s3, 
   fullemptyb_sync_pulse => feb,
   rport_dout_eop => ready,  
   osop => s1, oeop => s2, ovalid => s0, 
   rp_load => pointerload, rp_enb => pointerenb, rd_done => readerdone,
   rport_meb => portmeb, rport_web => portweb, rport_reb => portreb
);

--Test the normal data state
sclk <= not sclk after 50 ns; -- clock
s3 <= '1' after 60 ns, '0' after 5000 ns; -- rstb
feb <= '1' after 250 ns, '0' after 350 ns;
ready <= '1' after 750 ns;

--Test WFSM
--WFSM: writer_fsm port map(
--   wclk => sclk, rstb => s3, 
--   isop => s1, ieop => s2, ivalid => s0, 
--   fullemptyb => feb,
--   wp_load => pointerload, wp_enb => pointerenb,
--  iready => ready, wr_done => writedone,
--   wport_meb => portmeb, wport_web => portweb, wport_reb => portreb
--);

--Test the normal data state
--sclk <= not sclk after 50 ns;
--s0 <= '1' after 60 ns;   
--s1 <= '1' after 150 ns, '0' after 250 ns;
--s2 <= '1' after 550 ns, '0' after 650 ns;
--s3 <= '1' after 60 ns, '0' after 5000 ns;
--feb <= '1' after 60 ns;

--Test the onebyte state
--sclk <= not sclk after 50 ns;
--s0 <= '1' after 60 ns;   
--s1 <= '1' after 150 ns, '0' after 250 ns;
--s2 <= '1' after 150 ns, '0' after 250 ns;
--s3 <= '1' after 60 ns, '0' after 5000 ns;
--feb <= '1' after 60 ns;

--Test the nodata state
--sclk <= not sclk after 50 ns;
--s0 <= '1' after 60 ns, '0' after 250 ns, '1' after 450 ns;   
--s1 <= '1' after 150 ns, '0' after 250 ns;
--s2 <= '1' after 550 ns, '0' after 650 ns;
--s3 <= '1' after 60 ns, '0' after 5000 ns;
--feb <= '1' after 60 ns;

--Test the two sop event
--sclk <= not sclk after 50 ns;
--s0 <= '1' after 60 ns; 
--s1 <= '1' after 150 ns, '0' after 250 ns, '1' after 450 ns, '0' after 550 ns;
--s2 <= '1' after 650 ns, '0' after 750 ns;
--s3 <= '1' after 60 ns, '0' after 5000 ns;
--feb <= '1' after 60 ns;

END behavial;