sys_int.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

WARNING:Xst:1291 - FF/Latch <30> is unconnected in block <cntrl>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <cntrl>.
WARNING:Xst:1291 - FF/Latch <28> is unconnected in block <cntrl>.
WARNING:Xst:1291 - FF/Latch <29> is unconnected in block <cntrl>.
WARNING:Xst:1291 - FF/Latch <cntrl_31> is unconnected in block <sys_int>.
WARNING:Xst:1291 - FF/Latch <cntrl_30> is unconnected in block <sys_int>.
WARNING:Xst:1291 - FF/Latch <cntrl_7> is unconnected in block <sys_int>.
WARNING:Xst:1291 - FF/Latch <cntrl_28> is unconnected in block <sys_int>.
WARNING:Xst:1291 - FF/Latch <cntrl_29> is unconnected in block <sys_int>.

Optimizing unit <sys_int> ...
Loading device for application Xst from file '3s50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sys_int, actual ratio is 7.
FlipFlop ld_cnt_reg has been replicated 1 time(s)
FlipFlop Act_st_int_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop Act_st_int_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop Act_st_int_0 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sys_int.ngr
Top Level Output File Name         : sys_int
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 133

Macro Statistics :
# Registers                        : 36
#      1-bit register              : 33
#      3-bit register              : 1
#      32-bit register             : 2

Cell Usage :
# BELS                             : 5
#      GND                         : 1
#      LUT1                        : 2
#      LUT3_D                      : 1
#      VCC                         : 1
# FlipFlops/Latches                : 99
#      FDC                         : 2
#      FDCE                        : 81
#      FDPE                        : 10
#      FDR                         : 6
# Shifters                         : 32
#      SRL16                       : 32
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 130
#      IBUF                        : 35
#      OBUF                        : 95
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-4 

 Number of Slices:                      57  out of    768     7%  
 Number of Slice Flip Flops:            99  out of   1536     6%  
 Number of 4 input LUTs:                35  out of   1536     2%  
 Number of bonded IOBs:                130  out of    124   104% (*) 
 Number of GCLKs:                        1  out of      8    12%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk_i                              | BUFGP                  | 131   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.247ns (Maximum Frequency: 445.038MHz)
   Minimum input arrival time before clock: 5.732ns
   Maximum output required time after clock: 8.310ns
   Maximum combinational path delay: 7.045ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'Clk_i'
Delay:               2.247ns (Levels of Logic = 0)
  Source:            ld_cnt_reg (FF)
  Destination:       cntrl_20 (FF)
  Source Clock:      Clk_i rising
  Destination Clock: Clk_i rising

  Data Path: ld_cnt_reg to cntrl_20
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             14   0.720   0.925  ld_cnt_reg (ld_cnt_reg)
     FDCE:CE                   0.602          cntrl_2
    ----------------------------------------
    Total                      2.247ns (1.322ns logic, 0.925ns route)
                                       (58.8% logic, 41.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk_i'
Offset:              5.732ns (Levels of Logic = 2)
  Source:            data_addr_n_reg (PAD)
  Destination:       Add_reg_31 (FF)
  Destination Clock: Clk_i rising

  Data Path: data_addr_n_reg to Add_reg_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            39   1.930   1.328  data_addr_n_reg_IBUF (data_addr_n_reg_IBUF)
     LUT1:I0->O           32   0.551   1.321  Add_reg_ClkEn_INV1 (Add_reg_N233)
     FDCE:CE                   0.602          Add_reg_0
    ----------------------------------------
    Total                      5.732ns (3.083ns logic, 2.649ns route)
                                       (53.8% logic, 46.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk_i'
Offset:              8.310ns (Levels of Logic = 1)
  Source:            SRL16_31 (FF)
  Destination:       sd_data_reg<31> (PAD)
  Source Clock:      Clk_i rising

  Data Path: SRL16_31 to sd_data_reg<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16:CLK->Q          1   3.195   0.240  SRL16_31 (sd_data_reg_31_OBUF)
     OBUF:I->O                 4.875          sd_data_reg_31_OBUF (sd_data_reg<31>)
    ----------------------------------------
    Total                      8.310ns (8.070ns logic, 0.240ns route)
                                       (97.1% logic, 2.9% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               7.045ns (Levels of Logic = 2)
  Source:            we_rn_i (PAD)
  Destination:       write_st (PAD)

  Data Path: we_rn_i to write_st
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.930   0.240  we_rn_i_IBUF (write_st_OBUF)
     OBUF:I->O                 4.875          write_st_OBUF (write_st)
    ----------------------------------------
    Total                      7.045ns (6.805ns logic, 0.240ns route)
                                       (96.6% logic, 3.4% route)

=========================================================================
CPU : 23.35 / 27.72 s | Elapsed : 23.00 / 27.00 s
 
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Total memory usage is 65412 kilobytes