sys_int.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 2.18 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.18 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: sys_int.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sys_int.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sys_int
Output Format                      : NGC
Target Device                      : xc3s50-4-pq208

---- Source Options
Top Module Name                    : sys_int
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sys_int.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sys_int.vhd in Library work.
Architecture sys_int_arch of Entity sys_int is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sys_int> (Architecture <sys_int_arch>).
INFO:Xst:1561 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 67: Mux is complete : default of case is discarded
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 106: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 108: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 110: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 112: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 114: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 116: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 118: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 120: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 122: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 124: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 126: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 128: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 130: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 132: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 134: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 136: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 138: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 140: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 142: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 144: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 146: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 148: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 150: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 152: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 154: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 156: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 158: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 160: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 162: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 164: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 166: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 168: Generating a Black Box for component <SRL16>.
Entity <sys_int> analyzed. Unit <sys_int> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sys_int>.
    Related source file is C:/Xilinx/ise_work/buzhidao/sys_int.vhd.
WARNING:Xst:647 - Input <we_rn_reg> is never used.
WARNING:Xst:647 - Input <data_addr_n_i> is never used.
WARNING:Xst:1780 - Signal <addr> is never used or assigned.
WARNING:Xst:646 - Signal <cntrl<31:28>> is assigned but never used.
WARNING:Xst:646 - Signal <cntrl<7>> is assigned but never used.
    Found 32-bit register for signal <Add_reg>.
    Found 3-bit register for signal <Act_st_int>.
    Found 32-bit register for signal <cntrl>.
    Found 32-bit register for signal <Data_reg>.
    Found 1-bit register for signal <ld_cnt_reg>.
    Summary:
	inferred  68 D-type flip-flop(s).
Unit <sys_int> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
 32-bit register                   : 3
 1-bit register                    : 1
 3-bit register                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <31> is unconnected in block <cntrl>.