sdrmc_state.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: sdrmc_state.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sdrmc_state.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sdrmc_state
Output Format                      : NGC
Target Device                      : xc3s50-4-pq208

---- Source Options
Top Module Name                    : sdrmc_state
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sdrmc_state.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sdrmc_state.vhd in Library work.
Architecture sdrmc_state_arch of Entity sdrmc_state is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sdrmc_state> (Architecture <sdrmc_state_arch>).
Entity <sdrmc_state> analyzed. Unit <sdrmc_state> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sdrmc_state>.
    Related source file is C:/Xilinx/ise_work/buzhidao/sdrmc_state.vhd.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 38                                             |
    | Inputs             | 14                                             |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | Reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000000000001                                  |
    | Power Up State     | 0000000000001                                  |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <sdrmc_state> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 13
 1-bit register                    : 13

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <sdrmc_state> ...
Loading device for application Xst from file '3s50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sdrmc_state, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sdrmc_state.ngr
Top Level Output File Name         : sdrmc_state
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 24

Cell Usage :
# BELS                             : 33
#      LUT1                        : 1
#      LUT2                        : 7
#      LUT3                        : 5
#      LUT3_L                      : 3
#      LUT4                        : 7
#      LUT4_L                      : 10
# FlipFlops/Latches                : 13
#      FDC                         : 12
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 23
#      IBUF                        : 11
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-4 

 Number of Slices:                      19  out of    768     2%  
 Number of Slice Flip Flops:            13  out of   1536     0%  
 Number of 4 input LUTs:                33  out of   1536     2%  
 Number of bonded IOBs:                 23  out of    124    18%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 13    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.953ns (Maximum Frequency: 338.639MHz)
   Minimum input arrival time before clock: 4.954ns
   Maximum output required time after clock: 7.924ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'Clk'
Delay:               2.953ns (Levels of Logic = 2)
  Source:            state_FFd13 (FF)
  Destination:       state_FFd13 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: state_FFd13 to state_FFd13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              6   0.720   0.688  state_FFd13 (state_FFd13)
     LUT3:I0->O            1   0.551   0.240  state_FFd13-In47_SW0 (N2090)
     LUT4_L:I3->LO         1   0.551   0.000  state_FFd13-In47 (state_FFd13-In)
     FDP:D                     0.203          state_FFd13
    ----------------------------------------
    Total                      2.953ns (2.025ns logic, 0.928ns route)
                                       (68.6% logic, 31.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
Offset:              4.954ns (Levels of Logic = 4)
  Source:            Act_st<2> (PAD)
  Destination:       state_FFd11 (FF)
  Destination Clock: Clk rising

  Data Path: Act_st<2> to state_FFd11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             6   1.930   0.688  Act_st_2_IBUF (Act_st_2_IBUF)
     LUT4:I2->O            1   0.551   0.240  state_FFd13-In21 (CHOICE119)
     LUT3:I1->O            1   0.551   0.240  state_FFd13-In47_SW0 (N2090)
     LUT4_L:I3->LO         1   0.551   0.000  state_FFd13-In47 (state_FFd13-In)
     FDP:D                     0.203          state_FFd13
    ----------------------------------------
    Total                      4.954ns (3.786ns logic, 1.168ns route)
                                       (76.4% logic, 23.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
Offset:              7.924ns (Levels of Logic = 3)
  Source:            state_FFd12 (FF)
  Destination:       pre_sd_add_mx (PAD)
  Source Clock:      Clk rising

  Data Path: state_FFd12 to pre_sd_add_mx
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              8   0.720   0.747  state_FFd12 (state_FFd12)
     LUT3:I1->O            1   0.551   0.240  pre_sd_add_mx_SW0 (N1858)
     LUT4:I3->O            1   0.551   0.240  pre_sd_add_mx (pre_sd_add_mx_OBUF)
     OBUF:I->O                 4.875          pre_sd_add_mx_OBUF (pre_sd_add_mx)
    ----------------------------------------
    Total                      7.924ns (6.697ns logic, 1.227ns route)
                                       (84.5% logic, 15.5% route)

=========================================================================
CPU : 18.96 / 23.02 s | Elapsed : 19.00 / 23.00 s
 
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Total memory usage is 64388 kilobytes