sdrm.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 386: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 387: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 388: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 389: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 390: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 391: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 392: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 393: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 394: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 395: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 396: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 397: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 398: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 399: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 400: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 401: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 402: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 403: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 404: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 405: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 406: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 407: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 408: Generating a Black Box for component <IOBUF_F_12>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm.vhd line 409: Generating a Black Box for component <IOBUF_F_12>.
Entity <sdrm> analyzed. Unit <sdrm> generated.

Analyzing Entity <sdrm_t> (Architecture <sdrm_t_arch>).
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd line 186: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd line 191: Generating a Black Box for component <SRL16>.
INFO:Xst:1304 - Contents of register <sd_brst> in unit <sdrm_t> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <ad_tri_ref> in unit <sdrm_t> never changes during circuit operation. The register is replaced by logic.
Entity <sdrm_t> analyzed. Unit <sdrm_t> generated.

Analyzing Entity <sdrmc_state> (Architecture <sdrmc_state_arch>).
Entity <sdrmc_state> analyzed. Unit <sdrmc_state> generated.

Analyzing Entity <cslt_cntr> (Architecture <cslt_cntr_arch>).
Entity <cslt_cntr> analyzed. Unit <cslt_cntr> generated.

Analyzing Entity <brst_cntr> (Architecture <brst_cntr_arch>).
Entity <brst_cntr> analyzed. Unit <brst_cntr> generated.

Analyzing Entity <rcd_cntr> (Architecture <rcd_cntr_arch>).
Entity <rcd_cntr> analyzed. Unit <rcd_cntr> generated.

Analyzing Entity <ref_cntr> (Architecture <ref_cntr_arch>).
WARNING:Xst:819 - C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd line 27: The following signals are missing in the process sensitivity list:
   ref_max.
Entity <ref_cntr> analyzed. Unit <ref_cntr> generated.

Analyzing Entity <ki_cntr> (Architecture <ki_cntr_arch>).
Entity <ki_cntr> analyzed. Unit <ki_cntr> generated.

Analyzing generic Entity <sys_int> (Architecture <sys_int_arch>).
	ADDR_MSB = 31
	DATA_MSB = 31
	CYCLE = 8
	HALF_CYCLE = 4
INFO:Xst:1561 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 67: Mux is complete : default of case is discarded
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 106: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 108: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 110: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 112: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 114: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 116: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 118: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 120: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 122: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 124: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 126: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 128: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 130: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 132: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 134: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 136: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 138: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 140: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 142: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 144: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 146: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 148: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 150: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 152: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 154: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 156: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 158: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 160: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 162: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 164: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 166: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sys_int.vhd line 168: Generating a Black Box for component <SRL16>.
Entity <sys_int> analyzed. Unit <sys_int> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ki_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/ki_cntr.vhd.
    Found 4-bit subtractor for signal <$n0005> created at line 50.
    Found 4-bit register for signal <count>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Multiplexer(s).
Unit <ki_cntr> synthesized.


Synthesizing Unit <ref_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd.
    Found 1-bit register for signal <auto_ref>.
    Found 1-bit register for signal <p_auto_ref>.
    Found 16-bit subtractor for signal <$n0006> created at line 52.
    Found 16-bit register for signal <rcount>.
    Found 32 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred  32 Multiplexer(s).
Unit <ref_cntr> synthesized.


Synthesizing Unit <rcd_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/rcd_cntr.vhd.
    Found 2-bit subtractor for signal <$n0005> created at line 49.
    Found 2-bit register for signal <count>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Multiplexer(s).
Unit <rcd_cntr> synthesized.


Synthesizing Unit <brst_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/brst_cntr.vhd.
    Found 3-bit subtractor for signal <$n0007> created at line 47.
    Found 3-bit register for signal <count>.
    Found 3 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   3 Multiplexer(s).
Unit <brst_cntr> synthesized.


Synthesizing Unit <cslt_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/cslt_cntr.vhd.
    Found 2-bit subtractor for signal <$n0005> created at line 50.
    Found 2-bit register for signal <count>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Multiplexer(s).
Unit <cslt_cntr> synthesized.


Synthesizing Unit <sdrmc_state>.
    Related source file is C:/Xilinx/ise_work/buzhidao/sdrmc_state.vhd.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 38                                             |
    | Inputs             | 14                                             |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | Reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000000000001                                  |
    | Power Up State     | 0000000000001                                  |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <sdrmc_state> synthesized.


Synthesizing Unit <sys_int>.
    Related source file is C:/Xilinx/ise_work/buzhidao/sys_int.vhd.
WARNING:Xst:647 - Input <we_rn_reg> is never used.
WARNING:Xst:647 - Input <data_addr_n_i> is never used.
WARNING:Xst:1780 - Signal <addr> is never used or assigned.
WARNING:Xst:646 - Signal <cntrl<31:28>> is assigned but never used.
WARNING:Xst:646 - Signal <cntrl<7>> is assigned but never used.
    Found 32-bit register for signal <Add_reg>.
    Found 3-bit register for signal <Act_st_int>.
    Found 32-bit register for signal <cntrl>.
    Found 32-bit register for signal <Data_reg>.
    Found 1-bit register for signal <ld_cnt_reg>.