sdrm_t.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: sdrm_t.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : sdrm_t.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : sdrm_t
Output Format                      : NGC
Target Device                      : xc3s50-4-pq208

---- Source Options
Top Module Name                    : sdrm_t
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : ONLY
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sdrm_t.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sdrmc_state.vhd in Library work.
Architecture sdrmc_state_arch of Entity sdrmc_state is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/cslt_cntr.vhd in Library work.
Architecture cslt_cntr_arch of Entity cslt_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/brst_cntr.vhd in Library work.
Architecture brst_cntr_arch of Entity brst_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/rcd_cntr.vhd in Library work.
Architecture rcd_cntr_arch of Entity rcd_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd in Library work.
Architecture ref_cntr_arch of Entity ref_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/ki_cntr.vhd in Library work.
Architecture ki_cntr_arch of Entity ki_cntr is up to date.
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd in Library work.
Architecture sdrm_t_arch of Entity sdrm_t is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sdrm_t> (Architecture <sdrm_t_arch>).
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd line 186: Generating a Black Box for component <SRL16>.
WARNING:Xst:766 - C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd line 191: Generating a Black Box for component <SRL16>.
INFO:Xst:1304 - Contents of register <sd_brst> in unit <sdrm_t> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <ad_tri_ref> in unit <sdrm_t> never changes during circuit operation. The register is replaced by logic.
Entity <sdrm_t> analyzed. Unit <sdrm_t> generated.

Analyzing Entity <sdrmc_state> (Architecture <sdrmc_state_arch>).
Entity <sdrmc_state> analyzed. Unit <sdrmc_state> generated.

Analyzing Entity <cslt_cntr> (Architecture <cslt_cntr_arch>).
Entity <cslt_cntr> analyzed. Unit <cslt_cntr> generated.

Analyzing Entity <brst_cntr> (Architecture <brst_cntr_arch>).
Entity <brst_cntr> analyzed. Unit <brst_cntr> generated.

Analyzing Entity <rcd_cntr> (Architecture <rcd_cntr_arch>).
Entity <rcd_cntr> analyzed. Unit <rcd_cntr> generated.

Analyzing Entity <ref_cntr> (Architecture <ref_cntr_arch>).
WARNING:Xst:819 - C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd line 27: The following signals are missing in the process sensitivity list:
   ref_max.
Entity <ref_cntr> analyzed. Unit <ref_cntr> generated.

Analyzing Entity <ki_cntr> (Architecture <ki_cntr_arch>).
Entity <ki_cntr> analyzed. Unit <ki_cntr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ki_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/ki_cntr.vhd.
    Found 4-bit subtractor for signal <$n0005> created at line 50.
    Found 4-bit register for signal <count>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Multiplexer(s).
Unit <ki_cntr> synthesized.


Synthesizing Unit <ref_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd.
    Found 1-bit register for signal <auto_ref>.
    Found 1-bit register for signal <p_auto_ref>.
    Found 16-bit subtractor for signal <$n0006> created at line 52.
    Found 16-bit register for signal <rcount>.
    Found 32 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred  32 Multiplexer(s).
Unit <ref_cntr> synthesized.


Synthesizing Unit <rcd_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/rcd_cntr.vhd.
    Found 2-bit subtractor for signal <$n0005> created at line 49.
    Found 2-bit register for signal <count>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Multiplexer(s).
Unit <rcd_cntr> synthesized.


Synthesizing Unit <brst_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/brst_cntr.vhd.
    Found 3-bit subtractor for signal <$n0007> created at line 47.
    Found 3-bit register for signal <count>.
    Found 3 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   3 Multiplexer(s).
Unit <brst_cntr> synthesized.


Synthesizing Unit <cslt_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/cslt_cntr.vhd.
    Found 2-bit subtractor for signal <$n0005> created at line 50.
    Found 2-bit register for signal <count>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Multiplexer(s).
Unit <cslt_cntr> synthesized.


Synthesizing Unit <sdrmc_state>.
    Related source file is C:/Xilinx/ise_work/buzhidao/sdrmc_state.vhd.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 38                                             |
    | Inputs             | 14                                             |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | Reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000000000001                                  |
    | Power Up State     | 0000000000001                                  |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <sdrmc_state> synthesized.


Synthesizing Unit <sdrm_t>.
    Related source file is C:/Xilinx/ise_work/buzhidao/sdrm_t.vhd.
WARNING:Xst:646 - Signal <ad_tri_reg> is assigned but never used.
WARNING:Xst:646 - Signal <sd_brst> is assigned but never used.
WARNING:Xst:646 - Signal <ad_tri_ref> is assigned but never used.
    Found 11-bit register for signal <sd_add_o>.
    Found 1-bit register for signal <sd_ras_o>.
    Found 1-bit register for signal <sd_cas_o>.
    Found 1-bit register for signal <sd_we_o>.
    Found 1-bit register for signal <sd_ba_o>.
    Found 1-bit register for signal <ready_o>.
    Found 4-bit register for signal <sd_doe_n>.
    Found 1-bit register for signal <clr_ref_d>.
    Found 1-bit register for signal <ld_brst>.
    Found 1-bit register for signal <ld_cslt>.
    Found 1-bit register for signal <ld_rcd>.
    Found 1-bit register for signal <Locked_i_int>.
    Found 1-bit register for signal <sd_add_mx>.
    Found 11 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  26 D-type flip-flop(s).
	inferred  11 Multiplexer(s).
Unit <sdrm_t> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 5
 16-bit subtractor                 : 1
 3-bit subtractor                  : 1
 2-bit subtractor                  : 2
 4-bit subtractor                  : 1
# Registers                        : 33
 11-bit register                   : 1
 1-bit register                    : 26
 4-bit register                    : 2
 3-bit register                    : 1
 2-bit register                    : 2
 16-bit register                   : 1
# Multiplexers                     : 7
 11-bit 2-to-1 multiplexer         : 1
 2-bit 2-to-1 multiplexer          : 2
 3-bit 2-to-1 multiplexer          : 1
 16-bit 2-to-1 multiplexer         : 2
 4-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sdrm_t.ngr
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 82

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# FlipFlops/Latches                : 68
#      FD                          : 1
#      FDC                         : 23
#      FDCE                        : 1
#      FDCP                        : 16
#      FDE                         : 2
#      FDP                         : 1
#      FDR                         : 15
#      FDS                         : 9
=========================================================================
CPU : 33.78 / 43.22 s | Elapsed : 34.00 / 43.00 s
 
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Total memory usage is 57220 kilobytes