ref_cntr.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: ref_cntr.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ref_cntr.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : ref_cntr
Output Format                      : NGC
Target Device                      : xc3s50-4-pq208

---- Source Options
Top Module Name                    : ref_cntr
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ref_cntr.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd in Library work.
Architecture ref_cntr_arch of Entity ref_cntr is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ref_cntr> (Architecture <ref_cntr_arch>).
WARNING:Xst:819 - C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd line 27: The following signals are missing in the process sensitivity list:
   ref_max.
Entity <ref_cntr> analyzed. Unit <ref_cntr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ref_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/ref_cntr.vhd.
    Found 1-bit register for signal <auto_ref>.
    Found 1-bit register for signal <p_auto_ref>.
    Found 16-bit subtractor for signal <$n0006> created at line 52.
    Found 16-bit register for signal <rcount>.
    Found 32 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred  32 Multiplexer(s).
Unit <ref_cntr> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 16-bit subtractor                 : 1
# Registers                        : 3
 1-bit register                    : 2
 16-bit register                   : 1
# Multiplexers                     : 2
 16-bit 2-to-1 multiplexer         : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ref_cntr> ...
Loading device for application Xst from file '3s50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ref_cntr, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ref_cntr.ngr
Top Level Output File Name         : ref_cntr
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 21

Macro Statistics :
# Registers                        : 2
#      1-bit register              : 2
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 2
# Adders/Subtractors               : 1
#      16-bit subtractor           : 1

Cell Usage :
# BELS                             : 109
#      GND                         : 1
#      LUT1                        : 3
#      LUT1_L                      : 15
#      LUT2                        : 34
#      LUT3_L                      : 17
#      LUT4                        : 6
#      LUT4_D                      : 1
#      MUXCY                       : 15
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 18
#      FDCE                        : 1
#      FDCP                        : 16
#      FDE                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 20
#      IBUF                        : 18
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-4 

 Number of Slices:                      43  out of    768     5%  
 Number of Slice Flip Flops:            18  out of   1536     1%  
 Number of 4 input LUTs:                76  out of   1536     4%  
 Number of bonded IOBs:                 20  out of    124    16%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 18    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.223ns (Maximum Frequency: 191.461MHz)
   Minimum input arrival time before clock: 5.554ns
   Maximum output required time after clock: 5.835ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'Clk'
Delay:               5.223ns (Levels of Logic = 18)
  Source:            rcount_0 (FF)
  Destination:       rcount_15 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: rcount_0 to rcount_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q             5   0.720   0.658  rcount_0 (rcount_0)
     LUT1_L:I0->LO         1   0.551   0.000  rcount<0>_rt (rcount<0>_rt)
     MUXCY:S->O            1   0.500   0.000  ref_cntr__n0013<0>cy (ref_cntr__n0013<0>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<1>cy (ref_cntr__n0013<1>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<2>cy (ref_cntr__n0013<2>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<3>cy (ref_cntr__n0013<3>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<4>cy (ref_cntr__n0013<4>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<5>cy (ref_cntr__n0013<5>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<6>cy (ref_cntr__n0013<6>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<7>cy (ref_cntr__n0013<7>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<8>cy (ref_cntr__n0013<8>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<9>cy (ref_cntr__n0013<9>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<10>cy (ref_cntr__n0013<10>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<11>cy (ref_cntr__n0013<11>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<12>cy (ref_cntr__n0013<12>_cyo)
     MUXCY:CI->O           1   0.064   0.000  ref_cntr__n0013<13>cy (ref_cntr__n0013<13>_cyo)
     MUXCY:CI->O           0   0.064   0.000  ref_cntr__n0013<14>cy (ref_cntr__n0013<14>_cyo)
     XORCY:CI->O           1   0.904   0.240  ref_cntr__n0013<15>_xor (_n0013<15>)
     LUT3_L:I2->LO         1   0.551   0.000  Mmux__n0000_Result<15>1 (_n0000<15>)
     FDCP:D                    0.203          rcount_15
    ----------------------------------------
    Total                      5.223ns (4.325ns logic, 0.898ns route)
                                       (82.8% logic, 17.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
Offset:              5.554ns (Levels of Logic = 3)
  Source:            Reset (PAD)
  Destination:       rcount_15 (FF)
  Destination Clock: Clk rising

  Data Path: Reset to rcount_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            35   1.930   1.324  Reset_IBUF (Reset_IBUF)
     LUT4:I0->O           16   0.551   0.995  Ker15011 (N1503)
     LUT3_L:I0->LO         1   0.551   0.000  Mmux__n0000_Result<11>1 (_n0000<11>)
     FDCP:D                    0.203          rcount_11
    ----------------------------------------
    Total                      5.554ns (3.235ns logic, 2.319ns route)
                                       (58.2% logic, 41.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
Offset:              5.835ns (Levels of Logic = 1)
  Source:            auto_ref (FF)
  Destination:       auto_ref (PAD)
  Source Clock:      Clk rising

  Data Path: auto_ref to auto_ref
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.720   0.240  auto_ref (auto_ref_OBUF)
     OBUF:I->O                 4.875          auto_ref_OBUF (auto_ref)
    ----------------------------------------
    Total                      5.835ns (5.595ns logic, 0.240ns route)
                                       (95.9% logic, 4.1% route)

=========================================================================
CPU : 19.54 / 23.71 s | Elapsed : 20.00 / 24.00 s
 
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Total memory usage is 65412 kilobytes