fd_11.vhd.bak

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fd_11 is
    Port ( clk : in std_logic;
           d : in std_logic_vector(10 downto 0);
           q : out std_logic_vector(10 downto 0));
end fd_9;

architecture Behavioral of fd_11 is

begin
   process(clk)
	begin
	   if clk'event and clk='1'then
		     q<=d;
		end if;
   end process;
end Behavioral;