cslt_cntr.syr

这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：[e-mail]

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: cslt_cntr.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : cslt_cntr.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : cslt_cntr
Output Format                      : NGC
Target Device                      : xc3s50-4-pq208

---- Source Options
Top Module Name                    : cslt_cntr
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : cslt_cntr.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/Xilinx/ise_work/buzhidao/cslt_cntr.vhd in Library work.
Architecture cslt_cntr_arch of Entity cslt_cntr is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cslt_cntr> (Architecture <cslt_cntr_arch>).
Entity <cslt_cntr> analyzed. Unit <cslt_cntr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <cslt_cntr>.
    Related source file is C:/Xilinx/ise_work/buzhidao/cslt_cntr.vhd.
    Found 2-bit subtractor for signal <$n0005> created at line 50.
    Found 2-bit register for signal <count>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Multiplexer(s).
Unit <cslt_cntr> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 2-bit subtractor                  : 1
# Registers                        : 1
 2-bit register                    : 1
# Multiplexers                     : 1
 2-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <cslt_cntr> ...
Loading device for application Xst from file '3s50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block cslt_cntr, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cslt_cntr.ngr
Top Level Output File Name         : cslt_cntr
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 6

Macro Statistics :
# Registers                        : 1
#      2-bit register              : 1
# Multiplexers                     : 1
#      2-to-1 multiplexer          : 1

Cell Usage :
# BELS                             : 4
#      LUT1                        : 1
#      LUT2                        : 1
#      LUT4_L                      : 2
# FlipFlops/Latches                : 2
#      FDC                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      IBUF                        : 4
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-4 

 Number of Slices:                       2  out of    768     0%  
 Number of Slice Flip Flops:             2  out of   1536     0%  
 Number of 4 input LUTs:                 4  out of   1536     0%  
 Number of bonded IOBs:                  5  out of    124     4%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
Clk                                | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.051ns (Maximum Frequency: 487.567MHz)
   Minimum input arrival time before clock: 3.149ns
   Maximum output required time after clock: 6.963ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'Clk'
Delay:               2.051ns (Levels of Logic = 1)
  Source:            count_1 (FF)
  Destination:       count_1 (FF)
  Source Clock:      Clk rising
  Destination Clock: Clk rising

  Data Path: count_1 to count_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.720   0.577  count_1 (count_1)
     LUT4_L:I2->LO         1   0.551   0.000  Mmux__n0003_Result<0>1 (_n0003<0>)
     FDC:D                     0.203          count_0
    ----------------------------------------
    Total                      2.051ns (1.474ns logic, 0.577ns route)
                                       (71.9% logic, 28.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
Offset:              3.149ns (Levels of Logic = 2)
  Source:            ld_cslt (PAD)
  Destination:       count_1 (FF)
  Destination Clock: Clk rising

  Data Path: ld_cslt to count_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.930   0.465  ld_cslt_IBUF (ld_cslt_IBUF)
     LUT4_L:I0->LO         1   0.551   0.000  Mmux__n0003_Result<0>1 (_n0003<0>)
     FDC:D                     0.203          count_0
    ----------------------------------------
    Total                      3.149ns (2.684ns logic, 0.465ns route)
                                       (85.2% logic, 14.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
Offset:              6.963ns (Levels of Logic = 2)
  Source:            count_0 (FF)
  Destination:       cslt_end (PAD)
  Source Clock:      Clk rising

  Data Path: count_0 to cslt_end
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.720   0.577  count_0 (count_0)
     LUT2:I0->O            1   0.551   0.240  _n00041 (cslt_end_OBUF)
     OBUF:I->O                 4.875          cslt_end_OBUF (cslt_end)
    ----------------------------------------
    Total                      6.963ns (6.146ns logic, 0.817ns route)
                                       (88.3% logic, 11.7% route)

=========================================================================
CPU : 18.05 / 22.22 s | Elapsed : 18.00 / 22.00 s
 
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Total memory usage is 64388 kilobytes