test.vhw

这是我用vhdl语言

-- C:\XILINX\BIN\DPRAM2
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Sep 01 20:09:30 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test IS
END test;

ARCHITECTURE testbench_arch OF test IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT dpram2
		PORT (
			wr1 : In  std_logic;
			wr2 : In  std_logic;
			rd1 : In  std_logic;
			rd2 : In  std_logic;
			cs1 : In  std_logic;
			cs2 : In  std_logic;
			clk : In  std_logic;
			data1_in : In  std_logic_vector (7 DOWNTO 0);
			data2_in : In  std_logic_vector (7 DOWNTO 0);
			data1_out : Out  std_logic_vector (7 DOWNTO 0);
			data2_out : Out  std_logic_vector (7 DOWNTO 0);
			addr1 : In  std_logic_vector (4 DOWNTO 0);
			addr2 : In  std_logic_vector (4 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL wr1 : std_logic;
	SIGNAL wr2 : std_logic;
	SIGNAL rd1 : std_logic;
	SIGNAL rd2 : std_logic;
	SIGNAL cs1 : std_logic;
	SIGNAL cs2 : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL data1_in : std_logic_vector (7 DOWNTO 0);
	SIGNAL data2_in : std_logic_vector (7 DOWNTO 0);
	SIGNAL data1_out : std_logic_vector (7 DOWNTO 0);
	SIGNAL data2_out : std_logic_vector (7 DOWNTO 0);
	SIGNAL addr1 : std_logic_vector (4 DOWNTO 0);
	SIGNAL addr2 : std_logic_vector (4 DOWNTO 0);

BEGIN
	UUT : dpram2
	PORT MAP (
		wr1 => wr1,
		wr2 => wr2,
		rd1 => rd1,
		rd2 => rd2,
		cs1 => cs1,
		cs2 => cs2,
		clk => clk,
		data1_in => data1_in,
		data2_in => data2_in,
		data1_out => data1_out,
		data2_out => data2_out,
		addr1 => addr1,
		addr2 => addr2
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		clk <= transport '1';
		WAIT FOR 10 ns;
		WAIT FOR 40 ns;
		clk <= transport '0';
		WAIT FOR 40 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_data1_out(
			next_data1_out : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (data1_out /= next_data1_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns data1_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data1_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data1_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_data2_out(
			next_data2_out : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (data2_out /= next_data2_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns data2_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data2_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data2_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		wr1 <= transport '0';
		wr2 <= transport '0';
		rd1 <= transport '0';
		rd2 <= transport '0';
		cs1 <= transport '0';
		cs2 <= transport '0';
		data1_in <= transport std_logic_vector'("00000000"); --0
		data2_in <= transport std_logic_vector'("00000000"); --0
		addr1 <= transport std_logic_vector'("00000"); --0
		addr2 <= transport std_logic_vector'("00000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		wr1 <= transport '1';
		wr2 <= transport '1';
		cs1 <= transport '1';
		cs2 <= transport '1';
		data1_in <= transport std_logic_vector'("00000001"); --1
		data2_in <= transport std_logic_vector'("00001000"); --8
		addr1 <= transport std_logic_vector'("00001"); --1
		addr2 <= transport std_logic_vector'("10100"); --14
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		data1_in <= transport std_logic_vector'("00000010"); --2
		data2_in <= transport std_logic_vector'("00001001"); --9
		addr1 <= transport std_logic_vector'("00000"); --0
		addr2 <= transport std_logic_vector'("00000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		wr2 <= transport '0';
		rd2 <= transport '1';
		data1_in <= transport std_logic_vector'("00000011"); --3
		data2_in <= transport std_logic_vector'("00000000"); --0
		addr2 <= transport std_logic_vector'("00001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		data1_in <= transport std_logic_vector'("00000100"); --4
		addr2 <= transport std_logic_vector'("00000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		wr1 <= transport '0';
		wr2 <= transport '1';
		rd1 <= transport '1';
		rd2 <= transport '0';
		data2_in <= transport std_logic_vector'("00001010"); --A
		addr1 <= transport std_logic_vector'("10100"); --14
		addr2 <= transport std_logic_vector'("01000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		data2_in <= transport std_logic_vector'("00001011"); --B
		addr1 <= transport std_logic_vector'("00000"); --0
		addr2 <= transport std_logic_vector'("00000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		wr1 <= transport '0';
		wr2 <= transport '0';
		rd1 <= transport '0';
		rd2 <= transport '0';
		cs1 <= transport '0';
		cs2 <= transport '0';
		data2_in <= transport std_logic_vector'("00000000"); --0
		-- --------------------
		WAIT FOR 400 ns; -- Time=1100 ns
		cs1 <= transport '0';
		cs2 <= transport '0';
		-- --------------------
		WAIT FOR 110 ns; -- Time=1210 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION dpram2_cfg OF test IS
	FOR testbench_arch
	END FOR;
END dpram2_cfg;