📄 dpram2.mrp
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Release 6.1i Map G.23Xilinx Mapping Report File for Design 'dpram2'Design Information------------------Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s300e-pq208-6 -cm
area -pr b -k 4 -c 100 -tx off -o dpram2_map.ncd dpram2.ngd dpram2.pcf Target Device : x2s300eTarget Package : pq208Target Speed : -6Mapper Version : spartan2e -- $Revision: 1.16 $Mapped Date : Fri Aug 25 16:10:36 2006Design Summary--------------Number of errors: 0Number of warnings: 0Logic Utilization: Number of Slice Flip Flops: 329 out of 6,144 5% Number of 4 input LUTs: 3,535 out of 6,144 57%Logic Distribution: Number of occupied Slices: 1,905 out of 3,072 62% Number of Slices containing only related logic: 1,905 out of 1,905 100% Number of Slices containing unrelated logic: 0 out of 1,905 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 3,543 out of 6,144 57% Number used as logic: 3,535 Number used as a route-thru: 8 Number of bonded IOBs: 48 out of 142 33% Number of GCLKs: 1 out of 4 25% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 25,174Additional JTAG gate count for IOBs: 2,352Peak Memory Usage: 85 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || addr1<0> | IOB | INPUT | LVTTL | | | | | || addr1<1> | IOB | INPUT | LVTTL | | | | | || addr1<2> | IOB | INPUT | LVTTL | | | | | || addr1<3> | IOB | INPUT | LVTTL | | | | | || addr1<4> | IOB | INPUT | LVTTL | | | | | || addr2<0> | IOB | INPUT | LVTTL | | | | | || addr2<1> | IOB | INPUT | LVTTL | | | | | || addr2<2> | IOB | INPUT | LVTTL | | | | | || addr2<3> | IOB | INPUT | LVTTL | | | | | || addr2<4> | IOB | INPUT | LVTTL | | | | | || cs1 | IOB | INPUT | LVTTL | | | | | || cs2 | IOB | INPUT | LVTTL | | | | | || data1_in<0> | IOB | INPUT | LVTTL | | | | | || data1_in<1> | IOB | INPUT | LVTTL | | | | | || data1_in<2> | IOB | INPUT | LVTTL | | | | | || data1_in<3> | IOB | INPUT | LVTTL | | | | | || data1_in<4> | IOB | INPUT | LVTTL | | | | | || data1_in<5> | IOB | INPUT | LVTTL | | | | | || data1_in<6> | IOB | INPUT | LVTTL | | | | | || data1_in<7> | IOB | INPUT | LVTTL | | | | | || data1_out<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data1_out<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_in<0> | IOB | INPUT | LVTTL | | | | | || data2_in<1> | IOB | INPUT | LVTTL | | | | | || data2_in<2> | IOB | INPUT | LVTTL | | | | | || data2_in<3> | IOB | INPUT | LVTTL | | | | | || data2_in<4> | IOB | INPUT | LVTTL | | | | | || data2_in<5> | IOB | INPUT | LVTTL | | | | | || data2_in<6> | IOB | INPUT | LVTTL | | | | | || data2_in<7> | IOB | INPUT | LVTTL | | | | | || data2_out<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || data2_out<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || rd1 | IOB | INPUT | LVTTL | | | | | || rd2 | IOB | INPUT | LVTTL | | | | | || wr1 | IOB | INPUT | LVTTL | | | | | || wr2 | IOB | INPUT | LVTTL | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.⌨️ 快捷键说明
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