dpram2.par

这是我用vhdl语言

Constraints file: dpram2.pcf

Loading device database for application Par from file "dpram2_map.ncd".
   "dpram2" is an NCD, version 2.38, device xc2s300e, package pq208, speed -6
Loading device for application Par from file '2s300e.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.17 2003-06-19.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            48 out of 142    33%
      Number of LOCed External IOBs    0 out of 48      0%

   Number of SLICEs                 1905 out of 3072   62%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98c83c) REAL time: 2 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
.............................
Phase 5.8 (Checksum:103d642) REAL time: 5 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 5 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 11 secs 

Writing design to file dpram2.ncd.

Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 11 secs 


Phase 1: 13922 unrouted;       REAL time: 12 secs 

Phase 2: 13607 unrouted;       REAL time: 12 secs 

Phase 3: 5666 unrouted;       REAL time: 13 secs 

Phase 4: 0 unrouted;       REAL time: 15 secs 

Total REAL time to Router completion: 16 secs 
Total CPU time to Router completion: 15 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |  315   |  0.080     |  0.507      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 382


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.224
   The MAXIMUM PIN DELAY IS:                              10.107
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   7.999

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 11.00  d >= 11.00
   ---------   ---------   ---------   ---------   ---------   ---------
        6844        5513        1256         270          39           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 17 secs 
Total CPU time to PAR completion: 16 secs 

Peak Memory Usage:  81 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file dpram2.ncd.


PAR done.