dpram2.twr

这是我用vhdl语言

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml dpram2 dpram2.ncd -o
dpram2.twr dpram2.pcf


Design file:              dpram2.ncd
Physical constraint file: dpram2.pcf
Device,speed:             xc2s300e,-6 (PRODUCTION 1.17 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
addr1<0>    |   19.029(R)|   -5.322(R)|clk_BUFGP         |   0.000|
addr1<1>    |   17.981(R)|   -4.903(R)|clk_BUFGP         |   0.000|
addr1<2>    |   16.625(R)|   -3.704(R)|clk_BUFGP         |   0.000|
addr1<3>    |   17.321(R)|   -3.100(R)|clk_BUFGP         |   0.000|
addr1<4>    |   17.160(R)|   -5.342(R)|clk_BUFGP         |   0.000|
addr2<0>    |   18.950(R)|   -6.134(R)|clk_BUFGP         |   0.000|
addr2<1>    |   16.914(R)|   -5.026(R)|clk_BUFGP         |   0.000|
addr2<2>    |   16.696(R)|   -5.222(R)|clk_BUFGP         |   0.000|
addr2<3>    |   18.387(R)|   -4.264(R)|clk_BUFGP         |   0.000|
addr2<4>    |   18.923(R)|   -5.219(R)|clk_BUFGP         |   0.000|
cs1         |   23.773(R)|   -1.439(R)|clk_BUFGP         |   0.000|
cs2         |   23.533(R)|   -0.994(R)|clk_BUFGP         |   0.000|
data1_in<0> |   14.767(R)|   -1.432(R)|clk_BUFGP         |   0.000|
data1_in<1> |   10.877(R)|   -1.057(R)|clk_BUFGP         |   0.000|
data1_in<2> |   12.726(R)|   -2.549(R)|clk_BUFGP         |   0.000|
data1_in<3> |   11.874(R)|   -1.123(R)|clk_BUFGP         |   0.000|
data1_in<4> |   11.239(R)|   -1.938(R)|clk_BUFGP         |   0.000|
data1_in<5> |   11.206(R)|   -2.107(R)|clk_BUFGP         |   0.000|
data1_in<6> |   10.728(R)|   -2.140(R)|clk_BUFGP         |   0.000|
data1_in<7> |   12.054(R)|   -2.013(R)|clk_BUFGP         |   0.000|
data2_in<0> |   12.388(R)|   -2.145(R)|clk_BUFGP         |   0.000|
data2_in<1> |   11.652(R)|   -1.976(R)|clk_BUFGP         |   0.000|
data2_in<2> |   12.138(R)|   -2.240(R)|clk_BUFGP         |   0.000|
data2_in<3> |   12.311(R)|   -2.943(R)|clk_BUFGP         |   0.000|
data2_in<4> |   12.563(R)|   -2.047(R)|clk_BUFGP         |   0.000|
data2_in<5> |   13.649(R)|   -1.795(R)|clk_BUFGP         |   0.000|
data2_in<6> |   13.409(R)|   -1.960(R)|clk_BUFGP         |   0.000|
data2_in<7> |   14.370(R)|   -1.877(R)|clk_BUFGP         |   0.000|
rd1         |   23.021(R)|   -2.229(R)|clk_BUFGP         |   0.000|
rd2         |   23.271(R)|   -2.609(R)|clk_BUFGP         |   0.000|
wr1         |   24.100(R)|   -1.344(R)|clk_BUFGP         |   0.000|
wr2         |   23.043(R)|   -0.661(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
data1_out<0>|    8.765(R)|clk_BUFGP         |   0.000|
data1_out<1>|    9.368(R)|clk_BUFGP         |   0.000|
data1_out<2>|    9.424(R)|clk_BUFGP         |   0.000|
data1_out<3>|    8.677(R)|clk_BUFGP         |   0.000|
data1_out<4>|    8.998(R)|clk_BUFGP         |   0.000|
data1_out<5>|    9.916(R)|clk_BUFGP         |   0.000|
data1_out<6>|    9.453(R)|clk_BUFGP         |   0.000|
data1_out<7>|    9.631(R)|clk_BUFGP         |   0.000|
data2_out<0>|    9.820(R)|clk_BUFGP         |   0.000|
data2_out<1>|    9.830(R)|clk_BUFGP         |   0.000|
data2_out<2>|    8.273(R)|clk_BUFGP         |   0.000|
data2_out<3>|    9.141(R)|clk_BUFGP         |   0.000|
data2_out<4>|   10.180(R)|clk_BUFGP         |   0.000|
data2_out<5>|    9.589(R)|clk_BUFGP         |   0.000|
data2_out<6>|    9.124(R)|clk_BUFGP         |   0.000|
data2_out<7>|    9.069(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   22.906|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Aug 25 16:11:08 2006
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Peak Memory Usage: 66 MB