e10281.vhd

来自「TCM解码」· VHDL 代码 · 共 40 行

---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool.
--
---------------------------------------------------------------------------

---------------------------------------------------------------------------
-- Entity declaration of 'd10281'.
---------------------------------------------------------------------------
-- -------------------------------------------------------------
-- This ENTITY is automatically generated by EASE - do not edit.
-- -------------------------------------------------------------

LIBRARY ieee, work ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
USE work.pfec.ALL ;
USE work.d10281_pack.ALL ;

ENTITY d10281 IS
  PORT(
    reset_n   : IN     std_logic ;
    clk       : IN     std_logic ;
    field_sync: IN     std_logic ;
    viterbi_init : IN  std_logic;
    data_in   : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
    data_en   : IN     std_logic;
    data_out  : OUT    std_logic_vector(7 DOWNTO 0) ;
    data_valid: OUT    std_logic ;
    mem_dout  : OUT    std_logic_vector( 2*trellis_width-1 DOWNTO 0 ) ;
    mem1_we_n : OUT    std_logic ;
    mem1_din  : IN     std_logic_vector( 2*trellis_width-1 DOWNTO 0 ) ;
    mem2_din  : IN     std_logic_vector( 2*trellis_width-1 DOWNTO 0 ) ;
    mem_cs_n  : OUT    std_logic ;
    mem1_a    : OUT    std_logic_vector( traceback_addr_width+4-1 DOWNTO 0 );
    mem2_a    : OUT    std_logic_vector( traceback_addr_width+4-1 DOWNTO 0 );
    mem2_we_n : OUT    std_logic ) ;
END  d10281 ;