e10281_ph.vhd
来自「TCM解码」· VHDL 代码 · 共 48 行
VHD
48 行
----------------------------------------------------------------------------- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,-- the 'Entity Architecture Schematics Editor for VHDL' tool.---------------------------------------------------------------------------------------------------------------------------------------------------------- Entity declaration of 'd10281_ph'.----------------------------------------------------------------------------- Drawing number : D10281-- Drawing description : Viterbi decoder core-- -- --------------------------------------------------------------- This ENTITY is automatically generated by EASE - do not edit.-- -------------------------------------------------------------LIBRARY ieee, work ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;USE work.pfec.ALL ;USE work.d10281_pack.ALL ;ENTITY d10281_ph IS PORT( reset_n : IN std_logic ; clk_out : IN std_logic ; decision : IN decision_vector_type ; out_y : IN std_logic_vector( trellis_width-1 DOWNTO 0 ); dout : OUT std_logic_vector( 1 DOWNTO 0 ) ; dovalid : OUT std_logic ; trellis_index : OUT std_logic_vector( 3 DOWNTO 0 ); clk_out_enable : IN std_logic ; trellis_sel : IN std_logic_vector( 3 DOWNTO 0 ); trellis_count : IN std_logic_vector( 3 DOWNTO 0 ); mem_dout : OUT std_logic_vector( 2*trellis_width-1 DOWNTO 0 ); mem1_we_n : OUT std_logic ; mem1_din : IN std_logic_vector( 2*trellis_width-1 DOWNTO 0 ); mem_cs_n : OUT std_logic ; mem1_a : OUT std_logic_vector( traceback_addr_width+4-1 DOWNTO 0 ) ; mem2_a : OUT std_logic_vector( traceback_addr_width+4-1 DOWNTO 0 ) ; mem2_we_n : OUT std_logic ; mem2_din : IN std_logic_vector( 2*trellis_width-1 DOWNTO 0 ); viterbi_init : IN std_logic ) ;END d10281_ph ;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?