a10281_ed.vhd

来自「TCM解码」· VHDL 代码 · 共 38 行

-- Drawing number       : D10281
-- Drawing description  : Viterbi decoder core
--
-- Entity name          : D10281_ED
-- Short description    : Euclidean Distances calculation unit
-- Architecture(s)      : RTL
--
--

LIBRARY ieee, work ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all;
USE work.pfec.ALL ;
USE work.d10281_pack.ALL ;

ARCHITECTURE rtl OF d10281_ed IS

  SIGNAL tmp      : std_logic_vector( INPUT_WIDTH DOWNTO 0 ) ;
  SIGNAL tmp_sqr  : std_logic_vector( 2*INPUT_WIDTH+1 DOWNTO 0 ) ;

BEGIN

--===========================================================
-- Combinatorial
--===========================================================
  tmp       <= signed(data_x(INPUT_WIDTH-1) & data_x) 
               - signed(data_y(INPUT_WIDTH-1) & data_y);
  tmp_sqr   <= signed( tmp ) * signed( tmp );
  --data_out  <= tmp_sqr( 2*INPUT_WIDTH-2 DOWNTO 2*INPUT_WIDTH-branch_metric_bits-1 ) ;
--phoenix modified 05.09.25 for dcl_vsbsym[9:0]
--  data_out  <= ( OTHERS => '1' ) WHEN tmp_sqr( 2*INPUT_WIDTH-2 DOWNTO 2*INPUT_WIDTH-5 ) /= "00000" 
--               ELSE tmp_sqr( 2*INPUT_WIDTH-6 DOWNTO 2*INPUT_WIDTH-branch_metric_bits-5 ) ;
  data_out  <= ( OTHERS => '1' ) WHEN tmp_sqr( 2*INPUT_WIDTH-6 DOWNTO 2*INPUT_WIDTH-9 ) /= "0000" 
               ELSE tmp_sqr( 2*INPUT_WIDTH-10 DOWNTO 2*INPUT_WIDTH-branch_metric_bits-9 ) ;
  
    
END rtl ;