a10281_obf.vhd

TCM解码

-- Drawing number       : D10281
-- Drawing description  : Viterbi decoder core
--
-- Entity name          : D10281_OBF
-- Short description    : Trellis Decode output
-- Architecture(s)      : RTL
--
-- Description          :
--
-- 

ARCHITECTURE rtl OF d10281_obf IS
  TYPE    ts_buf_type  IS ARRAY (11 DOWNTO 0) OF std_logic_vector(1 DOWNTO 0);
--==========================================
-- Combinatorial signals
--==========================================


--==========================================
-- Registers
--==========================================

  SIGNAL ts_buf0    : ts_buf_type;
  SIGNAL ts_buf1    : ts_buf_type;
  SIGNAL ts_buf2    : ts_buf_type;
  SIGNAL ts_buf3    : ts_buf_type;
  SIGNAL ts_bufin   : ts_buf_type;
  SIGNAL ts_count   : std_logic_vector( 3 DOWNTO 0 );
  SIGNAL ts_comp    : std_logic;
  SIGNAL ts_zero    : std_logic;
  SIGNAL byte_count : std_logic_vector( 1 DOWNTO 0 );
  SIGNAL byte_zero  : std_logic;
  SIGNAL byte_zero_d1 : std_logic;
  SIGNAL out_count  : std_logic_vector( 3 DOWNTO 0 );
  SIGNAL out_12     : std_logic;
  SIGNAL ts_diff    : std_logic_vector( 11 DOWNTO 0 );
  SIGNAL data_diff  : std_logic;
  SIGNAL data_valid_i : std_logic;
  
  SIGNAL symbol_count : std_logic_vector(9 DOWNTO 0); --wang chao added 2005-12-26 17:06
  SIGNAL cntr_count   : std_logic_vector(1 DOWNTO 0);
  SIGNAL out_count_0  : std_logic_vector( 3 DOWNTO 0 );
  SIGNAL out_count_4  : std_logic_vector( 3 DOWNTO 0 );
  SIGNAL out_count_8  : std_logic_vector( 3 DOWNTO 0);
  SIGNAL out_count_tmp_0 : std_logic_vector( 3 DOWNTO 0);
  SIGNAL out_count_tmp_1 : std_logic_vector( 3 DOWNTO 0);
  SIGNAL out_count_tmp_2 : std_logic_vector( 3 DOWNTO 0);
  SIGNAL out_count_table : std_logic_vector( 3 DOWNTO 0);
  SIGNAL cntr_mux     : std_logic_vector(1  DOWNTO 0);
  SIGNAL seg_mux      : std_logic_vector(1  DOWNTO 0);
  SIGNAL cntr_seg_count : std_logic_vector (1 DOWNTO 0);
  SIGNAL symbol_cnt_comp : std_logic;
  SIGNAL symbol_cnt_216 : std_logic;
  SIGNAL symbol_cnt_420 : std_logic;
  SIGNAL symbol_cnt_624 : std_logic;
  SIGNAL cntr_cnt_comp : std_logic;
  SIGNAL num0_zero : std_logic;
  SIGNAL num4_zero : std_logic;
  SIGNAL num8_zero : std_logic;
  
  
  SIGNAL data_en_d1 : std_logic;
  SIGNAL data_en_d2 : std_logic;
  SIGNAL data_en_d3 : std_logic;
  SIGNAL data_en_d4 : std_logic;
  --SIGNAL data_valid : std_logic;
  
BEGIN
   

--===========================================================
-- Combinatorial
--===========================================================

  data_valid <= data_valid_i and data_en_d4;
  ts_comp    <= '1' WHEN ts_count = "1011"  -- 12 trellis
              ELSE '0';
  ts_zero    <= '1' WHEN ts_count = "0000"  
              ELSE '0';
  byte_zero  <= '1' WHEN byte_count = "00"  
              ELSE '0';
  out_12     <= '1' WHEN out_count = "1100"  -- 12 trellis
              ELSE '0';
  symbol_cnt_comp <= '1' WHEN symbol_count="1100111011" -- 827 symbols
              ELSE '0';
  symbol_cnt_216 <= '1' WHEN symbol_count="0011010111" -- 216 symbols
              ELSE '0';  
  symbol_cnt_420 <= '1' WHEN symbol_count="0110100011" -- 420 symbols
              ELSE '0';
  symbol_cnt_624 <= '1' WHEN symbol_count="1001101111" -- 624 symbols
              ELSE '0';
  cntr_cnt_comp <= '1' WHEN cntr_count="11" 
              ELSE '0';
  num0_zero <= '1' WHEN out_count_0="1011" 
              ELSE '0';            
  num4_zero <= '1' WHEN out_count_4="1011" 
              ELSE '0';
  num8_zero <= '1' WHEN out_count_8="1011" 
              ELSE '0';
  cntr_mux <= cntr_count WHEN out_12= '1'
              ELSE cntr_mux;
  seg_mux  <= cntr_seg_count WHEN out_12 ='1'
              ELSE seg_mux;
  
  data_diff  <= data_in( 1 ) xor ts_diff(conv_integer(unsigned(trellis_index)));
         
--===========================================================
-- clock 
--===========================================================
  ts_num : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        ts_count  <= (OTHERS => '0');
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        ts_count  <= (OTHERS => '0');
      ELSIF data_en = '1' THEN
        IF ts_comp = '1' THEN
          ts_count  <= (OTHERS => '0');
        ELSE
          ts_count  <= unsigned(ts_count)+ '1';
        END IF;

      END IF;
    END IF;
  END PROCESS ts_num;  

  byte_num : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        byte_count  <= (OTHERS => '0');
        ts_buf0     <= (OTHERS => "00");
        ts_buf1     <= (OTHERS => "00");
        ts_buf2     <= (OTHERS => "00");
        ts_buf3     <= (OTHERS => "00");
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        byte_count  <= (OTHERS => '0');
      ELSIF data_en_d1 = '1' THEN
        IF ts_zero = '1' THEN
          IF byte_count = "00" THEN
            ts_buf0  <= ts_bufin;
          ELSIF byte_count = "01" THEN
            ts_buf1  <= ts_bufin;
          ELSIF byte_count = "10" THEN
            ts_buf2  <= ts_bufin;
          ELSIF byte_count = "11" THEN
            ts_buf3  <= ts_bufin;
          END IF;
          byte_count  <= unsigned(byte_count) + '1';
        END IF;
      END IF;
    END IF;
  END PROCESS byte_num;  
  
   
  
  delay : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        data_en_d1  <= '0';
        data_en_d2  <= '0';
        data_en_d3  <= '0';
        data_en_d4  <= '0';
        byte_zero_d1 <= '0';
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        data_en_d1  <= '0';
        data_en_d2  <= '0';
        data_en_d3  <= '0';
        data_en_d4  <= '0';
        byte_zero_d1 <= '0';
      ELSE
        data_en_d1  <= data_en;
        data_en_d2  <= data_en_d1;
        data_en_d3  <= data_en_d2;
        data_en_d4  <= data_en_d3;
        byte_zero_d1 <= byte_zero;
      END IF;
    END IF;
  END PROCESS delay;  
  
  out_data : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        data_out   <= (OTHERS => '0');
        data_valid_i <= '0';
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        data_out   <= (OTHERS => '0');
        data_valid_i <= '0';
      ELSIF out_12 = '0' THEN
        data_valid_i <= '1';
        data_out   <= ts_buf0(conv_integer(unsigned(out_count_table))) 
                    & ts_buf1(conv_integer(unsigned(out_count_table))) 
                    & ts_buf2(conv_integer(unsigned(out_count_table))) 
                    & ts_buf3(conv_integer(unsigned(out_count_table)));
                      
                      
      ELSE
        data_out  <= (OTHERS => '0');
        data_valid_i <= '0';
      END IF;
    END IF;
  END PROCESS out_data;  

  diff: PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        ts_diff   <= (OTHERS => '0');
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        ts_diff   <= (OTHERS => '0');
      ELSIF data_en = '1' THEN
        ts_diff(conv_integer(unsigned(trellis_index)))   <= data_in(1);                      
      END IF;
    END IF;
  END PROCESS diff; 
     
  in_data : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        ts_bufin   <= (OTHERS => "00");
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        ts_bufin   <= (OTHERS => "00");
      ELSIF data_en = '1' THEN
        ts_bufin(conv_integer(unsigned(trellis_index)))   <= data_diff & data_in( 0 ) ;               
      END IF;
    END IF;
  END PROCESS in_data;

-- wang chao added this logic for the bug found in tcm_decoder 2005-12-26 17:05  
    symbol_num : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        symbol_count  <= (OTHERS => '0');
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        symbol_count  <= (OTHERS => '0');
      ELSIF (data_valid_i and data_en_d4) = '1' THEN
        IF symbol_cnt_comp = '1' THEN
          symbol_count  <= (OTHERS => '0');
        ELSE
          symbol_count  <= unsigned(symbol_count)+ '1';
        END IF;

      END IF;
    END IF;
  END PROCESS symbol_num;   

 cntr_group_num : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        cntr_count  <= (OTHERS => '0');
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        cntr_count  <= (OTHERS => '0');
      ELSIF (data_valid_i and data_en_d4) = '1' THEN
        IF cntr_cnt_comp = '1' THEN
          cntr_count  <= (OTHERS => '0');
        ELSIF (symbol_count = "1100111001") THEN
          cntr_count  <= unsigned(cntr_count)+ '1';
        ELSE 
          cntr_count <= cntr_count;
        END IF;

      END IF;
    END IF;
  END PROCESS cntr_group_num;
  
  cntr_segmnt_num : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        cntr_seg_count  <= (OTHERS => '0');
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        cntr_seg_count  <= (OTHERS => '0');
      ELSIF (data_valid_i and data_en_d4) = '1' THEN
        IF (symbol_cnt_216='1' or symbol_cnt_420='1' or symbol_cnt_624='1' or symbol_cnt_comp= '1' ) THEN
          cntr_seg_count  <= unsigned(cntr_seg_count)+ '1';       
        ELSE 
          cntr_seg_count <= cntr_seg_count;
        END IF;

      END IF;
    END IF;
  END PROCESS cntr_segmnt_num;
  
   

out_num8 : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        out_count_8  <= "0111";
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        out_count_8  <= "0111";
      ELSIF data_en_d2 = '1' THEN
        IF byte_zero = '1' AND byte_zero_d1 = '0' THEN
          out_count_8  <= "1000";
        ELSIF out_12 = '0' THEN
          IF num8_zero = '1' THEN
            out_count_8 <= "0000";
          ELSE
            out_count_8  <= unsigned(out_count_8) + '1';
          END IF;
        
        END IF;
      END IF;
    END IF;
  END PROCESS out_num8;
  
out_num4 : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        out_count_4  <= "0011";
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        out_count_4  <= "0011";
      ELSIF data_en_d2 = '1' THEN
        IF byte_zero = '1' AND byte_zero_d1 = '0' THEN
          out_count_4  <= "0100";
        ELSIF out_12 = '0' THEN
          IF num4_zero = '1' THEN
            out_count_4 <= "0000";
          ELSE  
            out_count_4  <= unsigned(out_count_4) + '1';
          END IF;
        
        END IF;
      END IF;
    END IF;
  END PROCESS out_num4;  

out_num0 : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        out_count_0  <= "0000";
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        out_count_0  <= "0000";
      ELSIF data_en_d2 = '1' THEN
        IF byte_zero = '1' AND byte_zero_d1 = '0' THEN
          out_count_0  <= "0000";
        ELSIF out_12 = '0' THEN
          IF num0_zero= '1' THEN  
            out_count_0 <= "0000";
          ELSE
            out_count_0  <= unsigned(out_count_0) + '1';
          END IF;
        
        END IF;
      END IF;
    END IF;
  END PROCESS out_num0;

 out_num : PROCESS (reset_n, clk_obf)
  BEGIN
    IF reset_n = '0' THEN
        out_count  <= "1100";
    ELSIF clk_obf'EVENT AND clk_obf = '1' THEN
      IF viterbi_init = '1' THEN
        out_count  <= "1100";
      ELSIF data_en_d2 = '1' THEN
        IF byte_zero = '1' AND byte_zero_d1 = '0' THEN
          out_count  <= "0000";
        ELSIF out_12 = '0' THEN
          out_count  <= unsigned(out_count) + '1';
        END IF;
      END IF;
    END IF;
  END PROCESS out_num;
  
  
  
  out_count_mux : PROCESS (out_count_tmp_0,out_count_tmp_1,out_count_tmp_2,cntr_mux)
  BEGIN
    CASE cntr_mux IS 
        WHEN "00" => out_count_table <=out_count_tmp_0;
        
        WHEN "01" => out_count_table <=out_count_tmp_1;
        
        WHEN "10" => out_count_table <=out_count_tmp_2;
        
        WHEN OTHERS => out_count_table <="0000"; 
    END CASE;
  END PROCESS out_count_mux;

  group_mux_0 : PROCESS (out_count_0,out_count_4,out_count_8,seg_mux)
  BEGIN
    CASE seg_mux IS 
        WHEN "00" => out_count_tmp_0 <=out_count_0;
        
        WHEN "01" => out_count_tmp_0 <=out_count_4;
        
        WHEN "10" => out_count_tmp_0 <=out_count_8;
        
        WHEN "11" => out_count_tmp_0 <=out_count_0;
        
        WHEN OTHERS =>  out_count_tmp_0<= "0000";
    END CASE;
  END PROCESS group_mux_0;

group_mux_1 : PROCESS (out_count_0,out_count_4,out_count_8,seg_mux)
  BEGIN
    CASE seg_mux IS 
        WHEN "00" => out_count_tmp_1 <=out_count_4;
        
        WHEN "01" => out_count_tmp_1 <=out_count_8;
        
        WHEN "10" => out_count_tmp_1 <=out_count_0;
        
        WHEN "11" => out_count_tmp_1 <=out_count_4;
        
        WHEN OTHERS =>  out_count_tmp_1<= "0000"; 
    END CASE;
  END PROCESS group_mux_1;

group_mux_2 : PROCESS (out_count_0,out_count_4,out_count_8,seg_mux)
  BEGIN
    CASE seg_mux IS 
        WHEN "00" => out_count_tmp_2 <=out_count_8;
        WHEN "01" => out_count_tmp_2 <=out_count_0; 
        WHEN "10" => out_count_tmp_2 <=out_count_4;  
        WHEN "11" => out_count_tmp_2 <=out_count_8;  
        WHEN OTHERS =>  out_count_tmp_2<= "0000"; 
    END CASE;
  END PROCESS group_mux_2;








-- wang chao added end     
END rtl ;