e10281_acs.vhd

来自「TCM解码」· VHDL 代码 · 共 35 行

-- Drawing description  : Viterbi decoder core
--
-- Entity name          : d10281_acs
-- Short description    : Add-Compare-Select unit
-- Architecture(s)      : rtl
--
-- Description          :
-- 
-- The Add-Compare-Select (ACS) unit is based on modulo arithmetic, thus
-- avoiding the need for any nasty "normalisation" maths.  Spilt out from
-- d10281_sm, for faster synthesis.
--
-- This code is based on extensive simulation with a 'C' model.

  LIBRARY ieee,work;
  USE ieee.std_logic_1164.ALL;

  USE work.d10281_pack.ALL ;


  ENTITY d10281_acs IS
    PORT (
      bm_from_a : IN  branch_metric_type;
      bm_from_b : IN  branch_metric_type;
      sm_from_a : IN  state_metric_type;
      sm_from_b : IN  state_metric_type;
      y_from_a  : IN  std_logic;
      y_from_b  : IN  std_logic;
      next_sm   : OUT state_metric_type;
      out_y     : OUT std_logic;
      decision  : OUT std_logic
    );  
  END d10281_acs;