a10281_bm.vhd

TCM解码

-- Drawing number       : D10281
-- Drawing description  : Viterbi decoder core
--
-- Entity name          : D10281_BM
-- Short description    : Branch metric calculation unit
-- Architecture(s)      : RTL
--
--

LIBRARY ieee, work ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all;
USE work.pfec.ALL ;
USE work.d10281_pack.ALL ;

ARCHITECTURE rtl OF d10281_bm IS

COMPONENT d10281_ed
  PORT(
    data_x          : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
    data_y          : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
    data_out        : OUT    branch_metric_type 
     ) ;
END  COMPONENT ;

  SIGNAL dgtn3  : BOOLEAN ;
  SIGNAL dgtn1  : BOOLEAN ; 
  SIGNAL dgt1   : BOOLEAN ;
  SIGNAL dgt3   : BOOLEAN ;
  SIGNAL count  : std_logic_vector(3 DOWNTO 0);
  SIGNAL bm0_mul : branch_metric_type ;
  SIGNAL bm1_mul : branch_metric_type ;
  SIGNAL bm2_mul : branch_metric_type ;
  SIGNAL bm3_mul : branch_metric_type ;
  SIGNAL data_i  : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
  SIGNAL data_zero_x    : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
  SIGNAL data_zero_y    : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
  SIGNAL data_one_x     : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
  SIGNAL data_one_y     : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
  SIGNAL data_zero_out  : branch_metric_type ;
  SIGNAL data_one_out   : branch_metric_type ;
  SIGNAL tre_sel        : std_logic_vector( 3 DOWNTO 0 );
  SIGNAL tre_count      : std_logic_vector( 3 DOWNTO 0 );
  
  

BEGIN


--===========================================================
-- Combinatorial
--===========================================================

  dgtn3 <= signed(data_i) >= signed(data_n3);
  dgtn1 <= signed(data_i) >= signed(data_n1);
  dgt3  <= signed(data_i) >= signed(data_3);
  dgt1  <= signed(data_i) >= signed(data_1);
  
    
  bm0 <= bm0_mul;
  bm1 <= bm1_mul;
  bm2 <= bm2_mul;
  bm3 <= bm3_mul;
  
  data_zero_x   <= data_i;
  data_one_x    <= data_i;
  
  U_zero_ed: d10281_ed
    PORT MAP(
      data_x    => data_zero_x,
      data_y    => data_zero_y,
      data_out  => data_zero_out
      );
 
  U_one_ed: d10281_ed
    PORT MAP(
      data_x    => data_one_x,
      data_y    => data_one_y,
      data_out  => data_one_out
      );     
      
  
  calc_in : PROCESS (count, data_i)
  BEGIN
        
    IF count(0) = '1' THEN
      data_zero_y    <= data_n7;
      data_one_y     <= data_1;
    ELSIF count(1) = '1' THEN
      data_zero_y    <= data_n5;
      data_one_y     <= data_3;
    ELSIF count(2) = '1' THEN
      data_zero_y    <= data_n3;
      data_one_y     <= data_5;
    ELSIF count(3) = '1' THEN
      data_zero_y    <= data_n1;
      data_one_y     <= data_7;
    ELSE
      data_zero_y    <= ( OTHERS => '0' );
      data_one_y     <= ( OTHERS => '0' );
    END IF;

  END PROCESS calc_in;  
  
--===========================================================
-- Clocked
--===========================================================

  clk_phase : PROCESS (clk_out, reset_n)
  BEGIN
    IF reset_n = '0' THEN
        -- need this for simulation start up
        count <= (OTHERS => '0');
    ELSIF clk_out'EVENT AND clk_out = '1' THEN

      IF viterbi_init = '1' THEN
        count <= (OTHERS => '0');
      ELSIF data_valid = '1'  THEN
        count <= "0001";
      ELSE
        count <= count(2 downto 0 ) & '0' ;
      END IF; -- clk_out_enable
    END IF;   -- clock

  END PROCESS clk_phase; 
  
  
  out_en : PROCESS (clk_out, reset_n)
  BEGIN
    IF reset_n = '0' THEN
        -- need this for simulation start up
        clk_out_enable <= '0';
    ELSIF clk_out'EVENT AND clk_out = '1' THEN

      IF viterbi_init = '1' THEN
        clk_out_enable <= '0';
      ELSE
        clk_out_enable <= count(3);
      END IF; -- clk_out_enable
    END IF;   -- clock

  END PROCESS out_en; 
  
  tre_d1 : PROCESS (clk_out, reset_n)
  BEGIN
    IF reset_n = '0' THEN
        -- need this for simulation start up
        tre_sel <= (OTHERS => '0');
        tre_count  <= (OTHERS => '0');
    ELSIF clk_out'EVENT AND clk_out = '1' THEN

      IF viterbi_init = '1' THEN
        tre_sel <= (OTHERS => '0');
        tre_count  <= (OTHERS => '0');
      ELSIF data_valid = '1' THEN
        tre_sel <= trellis_sel_in;
        tre_count  <= tre_count_in;
      END IF; -- clk_out_enable
    END IF;   -- clock

  END PROCESS tre_d1; 
  
  tre_out : PROCESS (clk_out, reset_n)
  BEGIN
    IF reset_n = '0' THEN
        -- need this for simulation start up
        trellis_sel_out <= (OTHERS => '0');
        tre_count_out  <= (OTHERS => '0');
    ELSIF clk_out'EVENT AND clk_out = '1' THEN

      IF viterbi_init = '1' THEN
        trellis_sel_out <= (OTHERS => '0');
        tre_count_out  <= (OTHERS => '0');
      ELSIF count(3) = '1' THEN
        trellis_sel_out <= tre_sel;
        tre_count_out  <= tre_count;
      END IF; -- clk_out_enable
    END IF;   -- clock

  END PROCESS tre_out;
  
  
  calc_bm : PROCESS (clk_out, reset_n)
  variable tmp  : std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
  BEGIN
    IF reset_n = '0' THEN
        -- need this for simulation start up
        bm3_mul <= (OTHERS => '0');
        bm2_mul <= (OTHERS => '0');
        bm1_mul <= (OTHERS => '0'); 
        bm0_mul <= (OTHERS => '0'); 
        data_y  <= (OTHERS => '0'); 
    ELSIF clk_out'EVENT AND clk_out = '1' THEN

      IF viterbi_init = '1' THEN
        bm3_mul <= (OTHERS => '0');
        bm2_mul <= (OTHERS => '0');
        bm1_mul <= (OTHERS => '0'); 
        bm0_mul <= (OTHERS => '0'); 
        data_y  <= (OTHERS => '0'); 
      ELSE
        
        IF count(0) = '1' THEN
          IF dgtn3 THEN     
             bm0_mul <= data_one_out;
             data_y(0)  <= '1';
          ELSE
             bm0_mul <= data_zero_out;
             data_y(0)  <= '0';
          END IF;
        ELSIF count(1) = '1' THEN
          IF dgtn1 THEN     
             bm1_mul <= data_one_out;
             data_y(1)  <= '1';
          ELSE
             bm1_mul <= data_zero_out;
             data_y(1)  <= '0';
          END IF;
        ELSIF count(2) = '1' THEN
          IF dgt1 THEN     
             bm2_mul <= data_one_out;
             data_y(2)  <= '1';
          ELSE
             bm2_mul <= data_zero_out;
             data_y(2)  <= '0';
          END IF;
        ELSIF count(3) = '1' THEN
          IF dgt3 THEN    
             bm3_mul <= data_one_out;
             data_y(3)  <= '1';
          ELSE
             bm3_mul <= data_zero_out;
             data_y(3)  <= '0';
          END IF;
        END IF;

      END IF; -- clk_out_enable
    END IF;   -- clock

  END PROCESS calc_bm;  

  delay_pro : PROCESS (clk_out, reset_n)
  BEGIN
    IF reset_n = '0' THEN
       data_i    <= ( OTHERS => '0' );
    ELSIF clk_out'EVENT AND clk_out = '1' THEN

      IF viterbi_init = '1' THEN
        data_i   <= ( OTHERS => '0' );
      ELSE
        data_i   <= xdata;
      END IF; 
    END IF;  

  END PROCESS delay_pro; 
    
END rtl ;