p10281_pack.vhd

TCM解码

-- Drawing number       : D10281
-- Drawing description  : Viterbi Decoder
--
-- Short description    : Definitions of types, etc
--
-- Description          :
-- 
-- A package containing definitions for the Viterbi module.
-- NOTE: Synthesis switches have their own package, d10281_opt.


LIBRARY IEEE;
USE     IEEE.std_logic_1164.ALL;
USE     IEEE.std_logic_arith.ALL;

LIBRARY work;
USE     work.pfec.ALL;


PACKAGE d10281_pack IS

-- ================================================================
-- CONSTANTS
-- ================================================================

-- Memory order is the number of shift register bits in the encoder.
  CONSTANT memory_order       : POSITIVE := 2;

-- The code Generator Polynomials for G1(X) and G2(Y)
  CONSTANT g1_x               : NATURAL := 8#4#; 
  CONSTANT g2_y               : NATURAL := 8#1#; 
  CONSTANT gs                 : std_logic_vector( memory_order-1 DOWNTO 0) := "10"; 
  
  -- There is a limit on the difference between the greatest and smallest
  -- State Metric at any time.  For the convolutional code used by DVB, and
  -- using modulo arithmetic, this means that we need at least this many bits
  -- in the state metric accumulators (see section 2.5 of s10330.doc):
  CONSTANT state_metric_bits  : NATURAL  := soft_decision_bits+3;
  CONSTANT sm_msb             : NATURAL  := state_metric_bits-1;
  SUBTYPE  sm_lsbs           IS NATURAL RANGE sm_msb-1 DOWNTO 0;
  CONSTANT branch_metric_bits : NATURAL  := soft_decision_bits;
  CONSTANT trellis_width      : POSITIVE := 2**memory_order;
  CONSTANT generator_x        : std_logic_vector(memory_order DOWNTO 0)
                                  := std_logic_vector(conv_unsigned(g1_x, memory_order+1));
  CONSTANT generator_y        : std_logic_vector(memory_order DOWNTO 0)
                                  := std_logic_vector(conv_unsigned(g2_y, memory_order+1));

-- ================================================================
-- REGISTER ACCESS CONSTANTS
-- ================================================================

-- Described as...
--CONSTANT <address of the register>
--  SUBTYPE  <bitfield within the register>
--  CONSTANT <single bit within the register>


-- ================================================================
-- TYPES
-- ================================================================

  SUBTYPE soft_decision_type   IS std_logic_vector(soft_decision_bits-1 DOWNTO 0);
  SUBTYPE decision_mul_type   IS std_logic_vector(INPUT_WIDTH*2-1 DOWNTO 0);

  SUBTYPE branch_metric_type   IS std_logic_vector(branch_metric_bits-1 DOWNTO 0);
  TYPE    branch_metric_table  IS ARRAY (3 DOWNTO 0) OF branch_metric_type;

  SUBTYPE state_metric_type    IS std_logic_vector (sm_msb DOWNTO 0);
  TYPE    state_metric_array   IS ARRAY ( trellis_width-1 DOWNTO 0 ) OF state_metric_type;
  TYPE    trellis_metric_array IS ARRAY ( 11 DOWNTO 0 ) OF state_metric_array;

  SUBTYPE decision_vector_type IS std_logic_vector(trellis_width-1 DOWNTO 0);

    -- define signal refence value
--phoenix 05.09.27 -112 -80 -48 -16 16 48 80 112
    CONSTANT data_1          : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "0000010000";
    CONSTANT data_3          : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "0000110000";  
    CONSTANT data_5          : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "0001010000";  
    CONSTANT data_7          : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "0001110000";                                                          
    CONSTANT data_n1         : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "1111110000";
    CONSTANT data_n3         : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "1111010000";  
    CONSTANT data_n5         : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "1110110000";  
    CONSTANT data_n7         : std_logic_vector(INPUT_WIDTH-1 DOWNTO 0)
                                  := "1110010000";                             


  SUBTYPE traceback_address_type IS STD_LOGIC_VECTOR(traceback_addr_width-1 DOWNTO 0);

-- ================================================================
-- FUNCTIONS
-- ================================================================

  -- Compare function for modulo-2^n state metrics
  FUNCTION greater(a : state_metric_type; b : state_metric_type) RETURN BOOLEAN;

-- The code Generator Polynomials for G1(X) and G2(Y)
  FUNCTION genx (state : std_logic_vector(memory_order-1 DOWNTO 0);
                 data : std_logic) RETURN std_logic;
 
  FUNCTION geny (state : std_logic_vector(memory_order-1 DOWNTO 0);
                    data : std_logic) RETURN std_logic;

END d10281_pack;



PACKAGE BODY d10281_pack IS

  FUNCTION biwise_xor  ( v : std_logic_vector ) RETURN std_logic IS
    VARIABLE result : std_logic;
  BEGIN
      result := '0';
      FOR i IN v'RANGE LOOP
          result := result XOR v(i);
      END LOOP;
      RETURN result;
  END biwise_xor;


  -- The code Generator Polynomials for G1(X) and G2(Y)
  -- Automatically generatied from the polynomials specified in the
  -- synthesis option file.
  FUNCTION genx (state : std_logic_vector(memory_order-1 DOWNTO 0);
                  data : std_logic) RETURN std_logic IS
  BEGIN
      RETURN biwise_xor((data & state) AND generator_x);
  END genx;

  FUNCTION geny (state : std_logic_vector(memory_order-1 DOWNTO 0);
                  data : std_logic) RETURN std_logic IS
  BEGIN
      RETURN biwise_xor((data & state) AND generator_y);
  END geny;


  -- Compare function for modulo-2^n state metrics
  FUNCTION greater(a : state_metric_type; b : state_metric_type) RETURN BOOLEAN IS
    VARIABLE lsb_result : BOOLEAN;
    VARIABLE msb_result : BOOLEAN;
  BEGIN
    lsb_result := unsigned(a(sm_lsbs)) > unsigned(b(sm_lsbs));
    msb_result := a(sm_msb) /= b(sm_msb);
    RETURN lsb_result XOR msb_result;
  END;

END d10281_pack;