e10281_bm.vhd

来自「TCM解码」· VHDL 代码 · 共 43 行

---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool.
--
---------------------------------------------------------------------------

---------------------------------------------------------------------------
-- Entity declaration of 'd10281_bm'.
---------------------------------------------------------------------------
-- Drawing number       : D10281
-- Drawing description  : Viterbi decoder core
-- 
-- -------------------------------------------------------------
-- This ENTITY is automatically generated by EASE - do not edit.
-- -------------------------------------------------------------

LIBRARY ieee, work ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
USE work.pfec.ALL ;
USE work.d10281_pack.ALL ;


ENTITY d10281_bm IS
  PORT(
    xdata          : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
    data_valid     : IN     std_logic;
    trellis_sel_in : IN     std_logic_vector( 3 DOWNTO 0 ) ;
    tre_count_in   : IN     std_logic_vector( 3 DOWNTO 0 ) ;
    bm0            : OUT    branch_metric_type ;
    bm1            : OUT    branch_metric_type ;
    bm2            : OUT    branch_metric_type ;
    bm3            : OUT    branch_metric_type ;
    data_y         : OUT    std_logic_vector( 3 DOWNTO 0 );
    clk_out        : IN     std_logic ;
    clk_out_enable : OUT    std_logic ;
    trellis_sel_out: OUT    std_logic_vector( 3 DOWNTO 0 ) ;
    tre_count_out  : OUT    std_logic_vector( 3 DOWNTO 0 ) ;
    reset_n        : IN     std_logic ;
    viterbi_init   : IN     std_logic ) ;
END  d10281_bm ;