trellis_encoder.v

ATSC发送端部分

module trellis_encoder(
                      tre_encd_in,
                      tre_encd_out_0,
                      tre_encd_out_1,
                      tre_encd_out_2,
                      tre_encd_out_3,
                      counter,
                      rst_n,
                      clk 
                       );
    input [7:0] tre_encd_in;
    input [3:0] counter;
    input rst_n;
    input clk;
   

    output [2:0] tre_encd_out_0;
    output [2:0] tre_encd_out_1;
    output [2:0] tre_encd_out_2;
    output [2:0] tre_encd_out_3;
    
    reg tre_encd_out_0_0;
    reg tre_encd_out_0_1;
    reg tre_encd_out_0_2;
    
    reg tre_encd_out_1_0;
    reg tre_encd_out_1_1;
    reg tre_encd_out_1_2;
    
    reg tre_encd_out_2_0;
    reg tre_encd_out_2_1;
    reg tre_encd_out_2_2;
    
    reg tre_encd_out_3_0;
    reg tre_encd_out_3_1;
    reg tre_encd_out_3_2;
    
    reg z2_dly;
    reg z0_dly;
    reg xor_dly;
    
    //reg y2_dly,z0_dly,z0,z0_dly_xor;
    reg [7:0] tre_encd_in_reg;
 
    wire [2:0] tre_encd_out_0;
    wire [2:0] tre_encd_out_1;
    wire [2:0] tre_encd_out_2;
    wire [2:0] tre_encd_out_3;
    
    wire x1,x2,z1,z2,z0,z0_dly_xor;
    assign x1=tre_encd_in_reg[6];
    assign x2=tre_encd_in_reg[7];
    assign z2=z2_dly ^ x2;
    assign z1=x1;
    assign z0=xor_dly;
    assign z0_dly_xor=x1 ^ z0_dly;
    
    
    assign tre_encd_out_0={tre_encd_out_0_2,tre_encd_out_0_1,tre_encd_out_0_0};
    assign tre_encd_out_1={tre_encd_out_1_2,tre_encd_out_1_1,tre_encd_out_1_0};
    assign tre_encd_out_2={tre_encd_out_2_2,tre_encd_out_2_1,tre_encd_out_2_0};
    assign tre_encd_out_3={tre_encd_out_3_2,tre_encd_out_3_1,tre_encd_out_3_0};
 
 //---logical description----------------------------   
    always @ (posedge clk)
    begin
     if (counter==4'd0)
       tre_encd_in_reg<=tre_encd_in;
     else
       tre_encd_in_reg<={tre_encd_in_reg[5:0],2'bxx};
    end
  
    always @ (posedge clk or negedge rst_n)
    begin
    if (~rst_n)
    z2_dly<=1'b0;
    else if (~(tre_encd_in===8'hxx) && (counter==4'd1 || counter==4'd2 || counter==4'd3 || counter==4'd4) )
    z2_dly<=z2;
    end   
    
    always @ (posedge clk or negedge rst_n)
    begin
    if (~rst_n)
    z0_dly<=1'b0;
    else if (~(tre_encd_in===8'hxx) && (counter==4'd1 || counter==4'd2 || counter==4'd3 || counter==4'd4) )
    z0_dly<=z0;
    end 
  
    always @ (posedge clk or negedge rst_n)
    begin
    if (~rst_n)
    xor_dly<=1'b0;
   else if (~(tre_encd_in===8'hxx) && (counter==4'd1 || counter==4'd2 || counter==4'd3 || counter==4'd4) )
    xor_dly<= z0_dly_xor;
    end
    
   always @ (posedge clk)
   begin
   if (counter==4'd1) begin
   tre_encd_out_0_2<= z2;
   tre_encd_out_0_1<= z1;
   tre_encd_out_0_0<= z0;
   end
   end

   always @ (posedge clk)
   begin                  
   if (counter==4'd2) begin    
   tre_encd_out_1_2<= z2;
   tre_encd_out_1_1<= z1;
   tre_encd_out_1_0<= z0;
   end
   end                   

   always @ (posedge clk)
   begin                  
   if (counter==4'd3)    begin
   tre_encd_out_2_2<= z2;
   tre_encd_out_2_1<= z1;
   tre_encd_out_2_0<= z0;
   end
   end
   
   
   always @ (posedge clk)
   begin                 
   if (counter==4'd4) begin    
   tre_encd_out_3_2<= z2;
   tre_encd_out_3_1<= z1;
   tre_encd_out_3_0<= z0;
   end
   end
   
   
   
endmodule