📄 trellis_top.v
字号:
.data_out_10(wire_data_interleaver_out_10),
.data_out_11(wire_data_interleaver_out_11),
.clk(clk),
.ctrl(wire_ctrl_out), //remind me here
.interleaver_counter_in(wire_ctrl_counter_out)
);
trellis_encoder trellis_encoder_0(
.tre_encd_in(wire_data_interleaver_out_0),
.tre_encd_out_0(wire_encod_0_out_0),
.tre_encd_out_1(wire_encod_0_out_1),
.tre_encd_out_2(wire_encod_0_out_2),
.tre_encd_out_3(wire_encod_0_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_1(
.tre_encd_in(wire_data_interleaver_out_1),
.tre_encd_out_0(wire_encod_1_out_0),
.tre_encd_out_1(wire_encod_1_out_1),
.tre_encd_out_2(wire_encod_1_out_2),
.tre_encd_out_3(wire_encod_1_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_2(
.tre_encd_in(wire_data_interleaver_out_2),
.tre_encd_out_0(wire_encod_2_out_0),
.tre_encd_out_1(wire_encod_2_out_1),
.tre_encd_out_2(wire_encod_2_out_2),
.tre_encd_out_3(wire_encod_2_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_3(
.tre_encd_in(wire_data_interleaver_out_3),
.tre_encd_out_0(wire_encod_3_out_0),
.tre_encd_out_1(wire_encod_3_out_1),
.tre_encd_out_2(wire_encod_3_out_2),
.tre_encd_out_3(wire_encod_3_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_4(
.tre_encd_in(wire_data_interleaver_out_4),
.tre_encd_out_0(wire_encod_4_out_0),
.tre_encd_out_1(wire_encod_4_out_1),
.tre_encd_out_2(wire_encod_4_out_2),
.tre_encd_out_3(wire_encod_4_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_5(
.tre_encd_in(wire_data_interleaver_out_5),
.tre_encd_out_0(wire_encod_5_out_0),
.tre_encd_out_1(wire_encod_5_out_1),
.tre_encd_out_2(wire_encod_5_out_2),
.tre_encd_out_3(wire_encod_5_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_6(
.tre_encd_in(wire_data_interleaver_out_6),
.tre_encd_out_0(wire_encod_6_out_0),
.tre_encd_out_1(wire_encod_6_out_1),
.tre_encd_out_2(wire_encod_6_out_2),
.tre_encd_out_3(wire_encod_6_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_7(
.tre_encd_in(wire_data_interleaver_out_7),
.tre_encd_out_0(wire_encod_7_out_0),
.tre_encd_out_1(wire_encod_7_out_1),
.tre_encd_out_2(wire_encod_7_out_2),
.tre_encd_out_3(wire_encod_7_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_8(
.tre_encd_in(wire_data_interleaver_out_8),
.tre_encd_out_0(wire_encod_8_out_0),
.tre_encd_out_1(wire_encod_8_out_1),
.tre_encd_out_2(wire_encod_8_out_2),
.tre_encd_out_3(wire_encod_8_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_9(
.tre_encd_in(wire_data_interleaver_out_9),
.tre_encd_out_0(wire_encod_9_out_0),
.tre_encd_out_1(wire_encod_9_out_1),
.tre_encd_out_2(wire_encod_9_out_2),
.tre_encd_out_3(wire_encod_9_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_10(
.tre_encd_in(wire_data_interleaver_out_10),
.tre_encd_out_0(wire_encod_10_out_0),
.tre_encd_out_1(wire_encod_10_out_1),
.tre_encd_out_2(wire_encod_10_out_2),
.tre_encd_out_3(wire_encod_10_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
trellis_encoder trellis_encoder_11(
.tre_encd_in(wire_data_interleaver_out_11),
.tre_encd_out_0(wire_encod_11_out_0),
.tre_encd_out_1(wire_encod_11_out_1),
.tre_encd_out_2(wire_encod_11_out_2),
.tre_encd_out_3(wire_encod_11_out_3),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.clk(clk)
);
demux output_demux(
.wire_encod_0_out_0(wire_encod_0_out_0),
.wire_encod_0_out_1(wire_encod_0_out_1),
.wire_encod_0_out_2(wire_encod_0_out_2),
.wire_encod_0_out_3(wire_encod_0_out_3),
.wire_encod_1_out_0(wire_encod_1_out_0),
.wire_encod_1_out_1(wire_encod_1_out_1),
.wire_encod_1_out_2(wire_encod_1_out_2),
.wire_encod_1_out_3(wire_encod_1_out_3),
.wire_encod_2_out_0(wire_encod_2_out_0),
.wire_encod_2_out_1(wire_encod_2_out_1),
.wire_encod_2_out_2(wire_encod_2_out_2),
.wire_encod_2_out_3(wire_encod_2_out_3),
.wire_encod_3_out_0(wire_encod_3_out_0),
.wire_encod_3_out_1(wire_encod_3_out_1),
.wire_encod_3_out_2(wire_encod_3_out_2),
.wire_encod_3_out_3(wire_encod_3_out_3),
.wire_encod_4_out_0(wire_encod_4_out_0),
.wire_encod_4_out_1(wire_encod_4_out_1),
.wire_encod_4_out_2(wire_encod_4_out_2),
.wire_encod_4_out_3(wire_encod_4_out_3),
.wire_encod_5_out_0(wire_encod_5_out_0),
.wire_encod_5_out_1(wire_encod_5_out_1),
.wire_encod_5_out_2(wire_encod_5_out_2),
.wire_encod_5_out_3(wire_encod_5_out_3),
.wire_encod_6_out_0(wire_encod_6_out_0),
.wire_encod_6_out_1(wire_encod_6_out_1),
.wire_encod_6_out_2(wire_encod_6_out_2),
.wire_encod_6_out_3(wire_encod_6_out_3),
.wire_encod_7_out_0(wire_encod_7_out_0),
.wire_encod_7_out_1(wire_encod_7_out_1),
.wire_encod_7_out_2(wire_encod_7_out_2),
.wire_encod_7_out_3(wire_encod_7_out_3),
.wire_encod_8_out_0(wire_encod_8_out_0),
.wire_encod_8_out_1(wire_encod_8_out_1),
.wire_encod_8_out_2(wire_encod_8_out_2),
.wire_encod_8_out_3(wire_encod_8_out_3),
.wire_encod_9_out_0(wire_encod_9_out_0),
.wire_encod_9_out_1(wire_encod_9_out_1),
.wire_encod_9_out_2(wire_encod_9_out_2),
.wire_encod_9_out_3(wire_encod_9_out_3),
.wire_encod_10_out_0(wire_encod_10_out_0),
.wire_encod_10_out_1(wire_encod_10_out_1),
.wire_encod_10_out_2(wire_encod_10_out_2),
.wire_encod_10_out_3(wire_encod_10_out_3),
.wire_encod_11_out_0(wire_encod_11_out_0),
.wire_encod_11_out_1(wire_encod_11_out_1),
.wire_encod_11_out_2(wire_encod_11_out_2),
.wire_encod_11_out_3(wire_encod_11_out_3),
.clk(clk),
.clk4x(clk_4x),
.counter(wire_ctrl_counter_out),
.rst_n(rst_n),
.symbol_out(wire_symbol_out)
);
mapper mapper (
.data_in(wire_symbol_out),
.data_out()
);
always @ (posedge clk_4x) begin
$fdisplay (result,"%d",trellis_top.mapper.data_out);
end
always @ (posedge clk)begin
if (wire_ctrl_counter_out==4'd1) begin
$fdisplay(interleaver_out_0,"%h",wire_data_interleaver_out_0);
$fdisplay(interleaver_out_1,"%h",wire_data_interleaver_out_1);
$fdisplay(interleaver_out_2,"%h",wire_data_interleaver_out_2);
$fdisplay(interleaver_out_3,"%h",wire_data_interleaver_out_3);
$fdisplay(interleaver_out_4,"%h",wire_data_interleaver_out_4);
$fdisplay(interleaver_out_5,"%h",wire_data_interleaver_out_5);
$fdisplay(interleaver_out_6,"%h",wire_data_interleaver_out_6);
$fdisplay(interleaver_out_7,"%h",wire_data_interleaver_out_7);
$fdisplay(interleaver_out_8,"%h",wire_data_interleaver_out_8);
$fdisplay(interleaver_out_9,"%h",wire_data_interleaver_out_9);
$fdisplay(interleaver_out_10,"%h",wire_data_interleaver_out_10);
$fdisplay(interleaver_out_11,"%h",wire_data_interleaver_out_11);
end
end
always @ (posedge clk_4x) begin
$fdisplay (symbol_out,"%h",wire_symbol_out);
end
endmodule ⌨️ 快捷键说明
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