trellis_top.v

ATSC发送端部分

`timescale 1ns/1ps
module trellis_top();
//-----------clock generate------
reg clk;
always #100 clk=~clk;

reg clk_4x;
always #25 clk_4x=~clk_4x;

//-----------reg declearation----
reg rst_n;
reg [7:0] data [650000:1];
reg [7:0] data_in_temp;
reg [20:0] counter;

integer result;

reg [7:0] interleaver_out_0;
reg [7:0] interleaver_out_1;
reg [7:0] interleaver_out_2;
reg [7:0] interleaver_out_3;
reg [7:0] interleaver_out_4;
reg [7:0] interleaver_out_5;
reg [7:0] interleaver_out_6;
reg [7:0] interleaver_out_7;
reg [7:0] interleaver_out_8;
reg [7:0] interleaver_out_9;
reg [7:0] interleaver_out_10;
reg [7:0] interleaver_out_11;

reg [2:0] symbol_out;










//reg [143:0] segment0,segment1,segment2;
//-----------wire declearation---

wire [7:0] wire_data_ctrl_out_0;
wire [7:0] wire_data_ctrl_out_1;
wire [7:0] wire_data_ctrl_out_2;
wire [7:0] wire_data_ctrl_out_3;
wire [7:0] wire_data_ctrl_out_4;
wire [7:0] wire_data_ctrl_out_5;
wire [7:0] wire_data_ctrl_out_6;
wire [7:0] wire_data_ctrl_out_7;
wire [7:0] wire_data_ctrl_out_8;
wire [7:0] wire_data_ctrl_out_9;
wire [7:0] wire_data_ctrl_out_10;
wire [7:0] wire_data_ctrl_out_11;

wire [7:0] wire_data_in=data_in_temp;

wire [7:0] wire_data_interleaver_out_0;
wire [7:0] wire_data_interleaver_out_1;
wire [7:0] wire_data_interleaver_out_2;
wire [7:0] wire_data_interleaver_out_3;
wire [7:0] wire_data_interleaver_out_4;
wire [7:0] wire_data_interleaver_out_5;
wire [7:0] wire_data_interleaver_out_6;
wire [7:0] wire_data_interleaver_out_7;
wire [7:0] wire_data_interleaver_out_8;
wire [7:0] wire_data_interleaver_out_9;
wire [7:0] wire_data_interleaver_out_10;
wire [7:0] wire_data_interleaver_out_11;

wire [3:0] wire_ctrl_counter_out;

wire [2:0] wire_encod_0_out_0;
wire [2:0] wire_encod_0_out_1;
wire [2:0] wire_encod_0_out_2;
wire [2:0] wire_encod_0_out_3;

wire [2:0] wire_encod_1_out_0;
wire [2:0] wire_encod_1_out_1;
wire [2:0] wire_encod_1_out_2;
wire [2:0] wire_encod_1_out_3;

wire [2:0] wire_encod_2_out_0;
wire [2:0] wire_encod_2_out_1;
wire [2:0] wire_encod_2_out_2;
wire [2:0] wire_encod_2_out_3;

wire [2:0] wire_encod_3_out_0;
wire [2:0] wire_encod_3_out_1;
wire [2:0] wire_encod_3_out_2;
wire [2:0] wire_encod_3_out_3;

wire [2:0] wire_encod_4_out_0;
wire [2:0] wire_encod_4_out_1;
wire [2:0] wire_encod_4_out_2;
wire [2:0] wire_encod_4_out_3;

wire [2:0] wire_encod_5_out_0;
wire [2:0] wire_encod_5_out_1;
wire [2:0] wire_encod_5_out_2;
wire [2:0] wire_encod_5_out_3;

wire [2:0] wire_encod_6_out_0;
wire [2:0] wire_encod_6_out_1;
wire [2:0] wire_encod_6_out_2;
wire [2:0] wire_encod_6_out_3;

wire [2:0] wire_encod_7_out_0;
wire [2:0] wire_encod_7_out_1;
wire [2:0] wire_encod_7_out_2;
wire [2:0] wire_encod_7_out_3;

wire [2:0] wire_encod_8_out_0;
wire [2:0] wire_encod_8_out_1;
wire [2:0] wire_encod_8_out_2;
wire [2:0] wire_encod_8_out_3;

wire [2:0] wire_encod_9_out_0;
wire [2:0] wire_encod_9_out_1;
wire [2:0] wire_encod_9_out_2;
wire [2:0] wire_encod_9_out_3;

wire [2:0] wire_encod_10_out_0;
wire [2:0] wire_encod_10_out_1;
wire [2:0] wire_encod_10_out_2;
wire [2:0] wire_encod_10_out_3;

wire [2:0] wire_encod_11_out_0;
wire [2:0] wire_encod_11_out_1;
wire [2:0] wire_encod_11_out_2;
wire [2:0] wire_encod_11_out_3;

wire [1:0] wire_ctrl_out;
wire [2:0] wire_symbol_out;
wire [3:0] wire_trellis_out;




//-------------testbench initial-------
initial
begin
$readmemh("./data",data);
result=$fopen("./result.asc");
 interleaver_out_0=$fopen("./interleaver_out_0.asc"); 
 interleaver_out_1=$fopen("./interleaver_out_1.asc"); 
 interleaver_out_2=$fopen("./interleaver_out_2.asc"); 
 interleaver_out_3=$fopen("./interleaver_out_3.asc"); 
 interleaver_out_4=$fopen("./interleaver_out_4.asc"); 
 interleaver_out_5=$fopen("./interleaver_out_5.asc"); 
 interleaver_out_6=$fopen("./interleaver_out_6.asc"); 
 interleaver_out_7=$fopen("./interleaver_out_7.asc"); 
 interleaver_out_8=$fopen("./interleaver_out_8.asc"); 
 interleaver_out_9=$fopen("./interleaver_out_9.asc"); 
interleaver_out_10=$fopen("./interleaver_out_10.asc");
interleaver_out_11=$fopen("./interleaver_out_11.asc");

symbol_out=$fopen("./symbol_out.asc");










clk=1'b0;
clk_4x=1'b1;
rst_n=1'b1;
//counter=21'd0;
#400 rst_n=1'b0;
#400 rst_n=1'b1;
end

always @ (posedge clk or negedge rst_n)
begin
  if (~rst_n)
    counter <= 21'd1;
  else begin
  counter <= counter +1'b1;
  data_in_temp<= data [counter];
  end
end



trellis_ctrl trellis_ctrl(
                    .clk(clk),
                    .rst_n(rst_n),
		    .data_in(wire_data_in),
                    .data_out_0(wire_data_ctrl_out_0),		    
                    .data_out_1(wire_data_ctrl_out_1),		   
                    .data_out_2(wire_data_ctrl_out_2),		   
                    .data_out_3(wire_data_ctrl_out_3),		   
                    .data_out_4(wire_data_ctrl_out_4),			
                    .data_out_5(wire_data_ctrl_out_5),			
                    .data_out_6(wire_data_ctrl_out_6),			
                    .data_out_7(wire_data_ctrl_out_7),	
                    .data_out_8(wire_data_ctrl_out_8),		
                    .data_out_9(wire_data_ctrl_out_9),		
                    .data_out_10(wire_data_ctrl_out_10),	
                    .data_out_11(wire_data_ctrl_out_11),
                    .ctrl_counter_out(wire_ctrl_counter_out),
                    .ctrl_out(wire_ctrl_out)
                    );





interleaver interleaver(
                   .data_in_0(wire_data_ctrl_out_0),
                   .data_in_1(wire_data_ctrl_out_1), 
                   .data_in_2(wire_data_ctrl_out_2), 
                   .data_in_3(wire_data_ctrl_out_3), 
                   .data_in_4(wire_data_ctrl_out_4), 
                   .data_in_5(wire_data_ctrl_out_5), 
                   .data_in_6(wire_data_ctrl_out_6), 
                   .data_in_7(wire_data_ctrl_out_7), 
                   .data_in_8(wire_data_ctrl_out_8), 
                   .data_in_9(wire_data_ctrl_out_9), 
                   .data_in_10(wire_data_ctrl_out_10),
                   .data_in_11(wire_data_ctrl_out_11),
                   
                   .data_out_0(wire_data_interleaver_out_0),
                   .data_out_1(wire_data_interleaver_out_1), 
                   .data_out_2(wire_data_interleaver_out_2), 
                   .data_out_3(wire_data_interleaver_out_3), 
                   .data_out_4(wire_data_interleaver_out_4), 
                   .data_out_5(wire_data_interleaver_out_5), 
                   .data_out_6(wire_data_interleaver_out_6), 
                   .data_out_7(wire_data_interleaver_out_7), 
                   .data_out_8(wire_data_interleaver_out_8), 
                   .data_out_9(wire_data_interleaver_out_9),