trellis_ctrl.v

ATSC发送端部分

module trellis_ctrl(clk,
                    rst_n,
				            data_in,
                    data_out_0,		    
                    data_out_1,		   
                    data_out_2,		   
                    data_out_3,		   
                    data_out_4,			
                    data_out_5,			
                    data_out_6,			
                    data_out_7,	
                    data_out_8,		
                    data_out_9,		
                    data_out_10,	
                    data_out_11,
                    ctrl_counter_out,
                    ctrl_out
                    );				
				
				
			
input [7:0] data_in;
input clk;
input rst_n;

output [7:0] data_out_0;
output [7:0] data_out_1;
output [7:0] data_out_2;
output [7:0] data_out_3;
output [7:0] data_out_4;
output [7:0] data_out_5;
output [7:0] data_out_6;
output [7:0] data_out_7;
output [7:0] data_out_8;
output [7:0] data_out_9;
output [7:0] data_out_10;
output [7:0] data_out_11;
output [3:0] ctrl_counter_out;
output [1:0] ctrl_out;


reg [3:0] counter;
reg [7:0] data_out_0;
reg [7:0] data_out_1;
reg [7:0] data_out_2;
reg [7:0] data_out_3;
reg [7:0] data_out_4;
reg [7:0] data_out_5;
reg [7:0] data_out_6;
reg [7:0] data_out_7;
reg [7:0] data_out_8;
reg [7:0] data_out_9;
reg [7:0] data_out_10;
reg [7:0] data_out_11;

reg [1:0] ctrl_out;



reg rst_n_dly;

wire  [3:0] ctrl_counter_out;
assign ctrl_counter_out=counter;

integer counter_interleaver;
integer attach;

always @ (posedge clk)
begin
rst_n_dly <= rst_n;
end


always @ (posedge clk or negedge rst_n_dly )
begin
  if (~rst_n_dly) begin
   counter = 4'd0;
   attach=0;
   counter_interleaver=0;
   ctrl_out=0;
   //attach=0;
  end
  else begin
  if (counter==4'd11)
    counter = 4'd0;
  else 
    counter = counter+1'b1;
  end
  
end

always @ (posedge clk )
begin
 case (counter)
 4'd1: data_out_0 <=data_in;
 4'd2: data_out_1 <=data_in;
 4'd3: data_out_2 <=data_in;
 4'd4: data_out_3 <=data_in;
 4'd5: data_out_4 <=data_in;
 4'd6: data_out_5 <=data_in;
 4'd7: data_out_6 <=data_in;
 4'd8: data_out_7 <=data_in;
 4'd9: data_out_8 <=data_in;
 4'd10:data_out_9 <=data_in;
 4'd11: data_out_10 <=data_in;
 4'd0: data_out_11 <=data_in; 
 endcase



end

always @ (posedge clk)
begin
  if (counter==4'd11 && ((counter_interleaver+1)*12+attach)<207 && ~(data_out_11===8'hx))
    counter_interleaver<= counter_interleaver+1;
  else if (counter==4'd11 && ((counter_interleaver+1)*12+attach)==207 && ~(data_out_11===8'hx)) begin
    counter_interleaver<= 0;
    attach<=0;
  end
  else if (counter==4'd11 && ((counter_interleaver+1)*12+attach)>207 && ~(data_out_11===8'hx)) begin
    counter_interleaver<=0;
    attach<=((counter_interleaver+1)*12+attach)-207;
  end
  else begin
  end
end

always @ (counter_interleaver)
begin
  if (counter_interleaver==0) begin
    //if (ctrl_out==2'd2)
    //  ctrl_out=2'b00;
    //else 
      ctrl_out=ctrl_out+1'b1;
  end
    
end



endmodule