interleaver.v

ATSC发送端部分

module interleaver(data_in_0,
                   data_in_1, 
                   data_in_2, 
                   data_in_3, 
                   data_in_4, 
                   data_in_5, 
                   data_in_6, 
                   data_in_7, 
                   data_in_8, 
                   data_in_9, 
                   data_in_10,
                   data_in_11,
                   
                   data_out_0,
                   data_out_1, 
                   data_out_2, 
                   data_out_3, 
                   data_out_4, 
                   data_out_5, 
                   data_out_6, 
                   data_out_7, 
                   data_out_8, 
                   data_out_9, 
                   data_out_10,
                   data_out_11,
                   
                   clk,
                   ctrl,
                   interleaver_counter_in
                   );
    input [7:0] data_in_0;
    input [7:0] data_in_1;
    input [7:0] data_in_2;
    input [7:0] data_in_3;
    input [7:0] data_in_4;
    input [7:0] data_in_5;
    input [7:0] data_in_6;
    input [7:0] data_in_7;
    input [7:0] data_in_8;
    input [7:0] data_in_9;
    input [7:0] data_in_10;
    input [7:0] data_in_11;
    
    input clk;
    input [1:0] ctrl ;
    input [3:0] interleaver_counter_in;
    
    output [7:0] data_out_0;
    output [7:0] data_out_1;
    output [7:0] data_out_2;
    output [7:0] data_out_3;
    output [7:0] data_out_4;
    output [7:0] data_out_5;
    output [7:0] data_out_6;
    output [7:0] data_out_7;
    output [7:0] data_out_8;
    output [7:0] data_out_9;
    output [7:0] data_out_10;
    output [7:0] data_out_11;
    
    reg [7:0] data_out_0;
    reg [7:0] data_out_1;
    reg [7:0] data_out_2;
    reg [7:0] data_out_3;
    reg [7:0] data_out_4;
    reg [7:0] data_out_5;
    reg [7:0] data_out_6;
    reg [7:0] data_out_7;
    reg [7:0] data_out_8;
    reg [7:0] data_out_9;
    reg [7:0] data_out_10;
    reg [7:0] data_out_11;
    
    always @ (posedge clk)
    begin
    if (interleaver_counter_in==4'hb)
    case (ctrl)
    2'b00:begin
        #1 data_out_0  <=  data_in_0;      
        #1 data_out_1  <=  data_in_1; 
        #1 data_out_2  <=  data_in_2; 
        #1 data_out_3  <=  data_in_3; 
        #1 data_out_4  <=  data_in_4; 
        #1 data_out_5  <=  data_in_5; 
        #1 data_out_6  <=  data_in_6; 
        #1 data_out_7  <=  data_in_7; 
        #1 data_out_8  <=  data_in_8; 
        #1 data_out_9  <=  data_in_9; 
        #1 data_out_10 <=  data_in_10;
        #1 data_out_11 <=  data_in_11;      
    end   
    2'b01:begin
        #1 data_out_0  <=  data_in_8; 
        #1 data_out_1  <=  data_in_9; 
        #1 data_out_2  <=  data_in_10;
        #1 data_out_3  <=  data_in_11;
        #1 data_out_4  <=  data_in_0;
        #1 data_out_5  <=  data_in_1;
        #1 data_out_6  <=  data_in_2;
        #1 data_out_7  <=  data_in_3;
        #1 data_out_8  <=  data_in_4;
        #1 data_out_9  <=  data_in_5;
        #1 data_out_10 <=  data_in_6;
        #1 data_out_11 <=  data_in_7;
    end   
    2'b10:begin
    	#1 data_out_0  <=  data_in_4; 
    	#1 data_out_1  <=  data_in_5; 
    	#1 data_out_2  <=  data_in_6; 
    	#1 data_out_3  <=  data_in_7; 
    	#1 data_out_4  <=  data_in_8; 
    	#1 data_out_5  <=  data_in_9; 
    	#1 data_out_6  <=  data_in_10;
    	#1 data_out_7  <=  data_in_11;
    	#1 data_out_8  <=  data_in_0;
    	#1 data_out_9  <=  data_in_1;
    	#1 data_out_10 <=  data_in_2;
    	#1 data_out_11 <=  data_in_3;
    	
    end
    2'b11:begin
    	#1 data_out_0  <=  data_in_0; 
    	#1 data_out_1  <=  data_in_1; 
    	#1 data_out_2  <=  data_in_2; 
    	#1 data_out_3  <=  data_in_3; 
    	#1 data_out_4  <=  data_in_4; 
    	#1 data_out_5  <=  data_in_5; 
    	#1 data_out_6  <=  data_in_6; 
    	#1 data_out_7  <=  data_in_7; 
    	#1 data_out_8  <=  data_in_8; 
    	#1 data_out_9  <=  data_in_9; 
    	#1 data_out_10 <=  data_in_10;
    	#1 data_out_11 <=  data_in_11;
    	
    end
    endcase
    end

endmodule