i2c_tbuf.v

RD1006--I2C与存储器的IP 代码及说明文档

//----------------------------------------------------------------------------
// 
//  Name:  i2c_tbuf.v   
// 
//  Description: Tri-state buffer module
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: [e-mail]
// 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps

module i2c_tbuf(data_o,
                data,
                cs_l,
                rd_wr_l,
                sda,
                scl,
                scl_pin,
                sda_pin);

//-------------------------------------------------------------------
// port list

input   [7:0]   data_o;
output  [7:0]   data;
input           cs_l;
input           rd_wr_l;
input           sda;
input           scl;

output          scl_pin;
output          sda_pin;

//-------------------------------------------------------------------
// wires

wire    [7:0]   data;
wire            scl_pin;
wire            sda_pin;

//-------------------------------------------------------------------
// tri-state buffers

assign data = (!cs_l && rd_wr_l) ? data_o : 8'bz;

assign scl_pin = scl ? 1'bz : 1'b0;
                  
assign sda_pin = sda ? 1'bz : 1'b0;
                  
endmodule

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