i2c_wreg.v

RD1006--I2C与存储器的IP 代码及说明文档

//----------------------------------------------------------------------------
//-- 
//--  Name:  i2c_wreg.v   
//-- 
//--  Description: Write regiter module of I2C serial controller
//-- 
//--  $Revision: 1.0 $          
//--  
//--  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//--
//----------------------------------------------------------------------------
//-- Permission:
//--
//--   Lattice Semiconductor grants permission to use this code for use
//--   in synthesis for any Lattice programmable logic product.  Other
//--   use of this code, including the selling or duplication of any
//--   portion is strictly prohibited.
//--
//-- Disclaimer:
//--
//--   This VHDL or Verilog source code is intended as a design reference
//--   which illustrates how these types of functions can be implemented.
//--   It is the user's responsibility to verify their design for
//--   consistency and functionality through the use of formal
//--   verification methods.  Lattice Semiconductor provides no warranty
//--   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//--
//--    Lattice Semiconductor Corporation
//--    5555 NE Moore Court
//--    Hillsboro, OR 97124
//--    U.S.A
//--
//--    TEL: 1-800-Lattice (USA and Canada)
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//--    web: http://www.latticesemi.com/
//--    email: [e-mail]
//-- 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps


module i2c_wreg(data,
                addr,
                rst_l,
                clock,
                cs_l,
                rd_wr_l,
                scl_cnt_en,
                reg_clk_in,
                reg_clk_out,
                wrd_add,
                i2c_go,
                ack_l);

//---------------------------------------------------------------------
// port list

input   [7:0]   data;               // cpu data bus
input   [1:0]   addr;               // cpu address bus
input           rst_l;              // reset signal
input           clock;              // cpu clock
input           cs_l;               // chip select
input           rd_wr_l;            // read /write
input           scl_cnt_en;         // scl count enable -- clears go
input           reg_clk_in;         // reg write clock input

output          reg_clk_out;        // reg write clock out     
output  [7:0]   wrd_add;            // word address
output          i2c_go;             // i2c start cycle
output          ack_l;              // cpu acknowledge

//---------------------------------------------------------------------
// registers

reg             reg_clk_out;        // reg write clock out
reg     [7:0]   wrd_add;            // word address
reg             i2c_go;             // i2c start cycle
reg             ack_l;              // cpu acknowledge

//---------------------------------------------------------------------
// parameters

parameter w_add = 2'b00;            // word address register
parameter d_add = 2'b01;            // data register
parameter s_add = 2'b10;            // status register

//---------------------------------------------------------------------
// equations


// generate product term clock just in case I want to use input regs.
always @(posedge clock or negedge rst_l)
    if (!rst_l)
        reg_clk_out <= #1 1'b0;
    else if (!cs_l && !rd_wr_l && (addr == w_add))
        reg_clk_out <= #1 1'b1;
    else
        reg_clk_out <= #1 1'b0;
       
// If I don't want to use input regs, comment this code out.
always @(posedge reg_clk_in)
        wrd_add <= #1 data;
  
/*
// If I want to use input regs, comment this code out.
always @(posedge clock or negedge rst_l)
    if (!rst_l)
        wrd_add <= #1 8'b0;
    else if (!cs_l && !rd_wr_l && (addr == w_add))
        wrd_add <= #1 data;     
  */
  
always @(posedge clock or negedge rst_l)
    if (!rst_l)
        i2c_go <= #1 1'b0;
    else if (!cs_l && !rd_wr_l && (addr == w_add))
        i2c_go <= #1 1'b1;
    else if (scl_cnt_en)
        i2c_go <= #1 1'b0;
  
// send ack right back  
always @(posedge clock or negedge rst_l)
    if (!rst_l)
        ack_l <= #1 1'b1;
    else if (!cs_l)
        ack_l <= #1 1'b0;
    else
        ack_l <= #1 1'b1;
  
endmodule        

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