i2c_rreg.v

RD1006--I2C与存储器的IP 代码及说明文档

//----------------------------------------------------------------------------
// 
//  Name:  i2c_rreg.v   
// 
//  Description: Read register module of the I2C serial controller
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: [e-mail]
// 
//----------------------------------------------------------------------------

`timescale 1 ns /  100 ps

module i2c_rreg(wrd_add,
                i2c_rdata,
                i2c_rdy,
                i2c_act,
                ack_err,
                addr,
                data_o);

//-------------------------------------------------------------------
// port list

input   [7:0]   wrd_add;            // i2c word address
input   [7:0]   i2c_rdata;          // i2c read data
input           i2c_rdy;            // i2c status bit
input           i2c_act;            // i2c cycle active
input           ack_err;            // ack error
input   [1:0]   addr;               // cpu address
     
output  [7:0]   data_o;             // muxed cpu data output

//-------------------------------------------------------------------
// registers

reg     [7:0]   data_o;             // muxed cpu data output

//-------------------------------------------------------------------
// parameters

parameter w_add = 2'b00;           // word address register
parameter d_add = 2'b01;           // data register
parameter s_add = 2'b10;           // status register

//-------------------------------------------------------------------
// data mux


always @(addr or wrd_add or ack_err or i2c_rdata or i2c_rdy)
    
    case(addr)
        
        w_add   : data_o <= #1 wrd_add;
        d_add   : data_o <= #1 i2c_rdata;
        s_add   : data_o <= #1 {i2c_rdy,ack_err,5'b0,i2c_act};                                
        default : data_o <= #1 {i2c_rdy,ack_err,5'b0,i2c_act};
        endcase                              
    
endmodule        

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