i2c_clk.v

RD1006--I2C与存储器的IP 代码及说明文档

//----------------------------------------------------------------------------
// 
//  Name:  i2c_clk.v   
// 
//  Description: Clock Generation module of the I2C serial controller
// 
//  $Revision: 1.0 $          
//  
//  Copyright 2004 Lattice Semiconductor Corporation.  All rights reserved.
//
//----------------------------------------------------------------------------
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//----------------------------------------------------------------------------
//
//    Lattice Semiconductor Corporation
//    5555 NE Moore Court
//    Hillsboro, OR 97124
//    U.S.A
//
//    TEL: 1-800-Lattice (USA and Canada)
//    408-826-6000 (other locations)
//
//    web: http://www.latticesemi.com/
//    email: [e-mail]
// 
//----------------------------------------------------------------------------


`timescale 1 ns /  100 ps

/*
Module  i2c_clk
This module provides a programmable clock output for the I2C interface.
*/

module i2c_clk( clock,
                rst_l,
                scl_cnt_en,
                scl_tick);
                
//-------------------------------------------------------------------
// port list

input           clock;              // 50 MHz microprocessor clock
input           rst_l;              // low going reset from ext. world
input           scl_cnt_en;         // counter enable

output          scl_tick;           // 5 usec clock tick

//-------------------------------------------------------------------
// registers & wires

reg             scl_tick;           // 5 usec clock tick        

reg     [7:0]   cntr;               // divide counter

//-------------------------------------------------------------------
// code

// counter
always @(posedge clock or negedge rst_l)
    if (!rst_l)
        cntr <= #1 8'b0;
    else if (scl_cnt_en)    
        cntr <= #1 cntr + 1;            
    else
        cntr <= 8'b0;
        
always @(posedge clock or negedge rst_l)
    if (!rst_l)
        scl_tick <= #1 1'b0;
    else if (cntr == 8'hff)
        scl_tick <= #1 1'b1;
    else
        scl_tick <= #1 1'b0;
               
endmodule

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