blkram_gpio.vhd

ULTRACTR的源码

--*****************************************************************************
--	Module: BlockRAM GPIO Interface
--*****************************************************************************
--
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--     FOR A PARTICULAR PURPOSE.
--     
--     (c) Copyright 2002 Xilinx, Inc.
--     All rights reserved.
-- 
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Filename:     blkram_gpio.v
-- 
-- Description:    
-- Module creates a 32 bit input and 32 bit latched output via a block ram interface
--	bram address 0 = data to be written to GPIO (read from BRAM)
--  bram address 4 = data read from GPIO (write to BRAM address)
--
-- Design Notes:
-- 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author:  APD/SEG
-- History: 2003.08.08 - initial release
-- 
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- synthesis translate_off
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on


--/////////////////////////////////////////////////////////////////////////////

-- Module Declaration

--/////////////////////////////////////////////////////////////////////////////


ENTITY uc_gpio_ref IS
   GENERIC (
      --/////////////////////////////////////////////////////////////////////////////
      -- PARAMETER DECLARATION
      --/////////////////////////////////////////////////////////////////////////////
      C_FAMILY                       :  string(1 TO 8) := "virtex2p";    
      C_NUM_WE                       :  integer := 4;    
      C_PORT_DWIDTH                  :  integer := 32;    
      C_PORT_AWIDTH                  :  integer := 32);
   PORT (
      UC_Rst                  : IN std_logic;   
      UC_Clk                  : IN std_logic;   
      UC_GPIO_Dout_A          : OUT std_logic_vector(0 TO C_PORT_DWIDTH - 1);   
      UC_GPIO_Din_A           : IN std_logic_vector(0 TO C_PORT_DWIDTH - 1);   
      UC_BRAM_Rst_B           : OUT std_logic;   
      UC_BRAM_Clk_B           : OUT std_logic;   
      UC_BRAM_EN_B            : OUT std_logic;   
      UC_BRAM_WEN_B           : OUT std_logic_vector(0 TO C_NUM_WE - 1);   
      UC_BRAM_Addr_B          : OUT std_logic_vector(0 TO C_PORT_AWIDTH - 1);   
      UC_BRAM_Din_B           : IN std_logic_vector(0 TO C_PORT_DWIDTH - 1);   
      UC_BRAM_Dout_B          : OUT std_logic_vector(0 TO C_PORT_DWIDTH - 1));   
END ENTITY uc_gpio_ref;

ARCHITECTURE translated OF uc_gpio_ref IS


   --/////////////////////////////////////////////////////////////////////////////
   -- Signal Declaration
   --/////////////////////////////////////////////////////////////////////////////
   SIGNAL bram_wr                  :  std_logic;   
   SIGNAL temp_BRAM_WEN_B          :  std_logic_vector(0 TO C_NUM_WE - 1);   
   -- block ram address 4 for writes and 0 for reads
   SIGNAL temp_xhdl8               :  std_logic_vector(3 DOWNTO 0);   
   -- set write enables equal to 1 when writing to RAM	
   SIGNAL temp_xhdl9               :  std_logic_vector(31 DOWNTO 0);   
   SIGNAL UC_GPIO_Dout_A_xhdl1     :  std_logic_vector(0 TO C_PORT_DWIDTH - 1);   
   SIGNAL UC_BRAM_Rst_B_xhdl2      :  std_logic;   
   SIGNAL UC_BRAM_Clk_B_xhdl3      :  std_logic;   
   SIGNAL UC_BRAM_EN_B_xhdl4       :  std_logic;   
   SIGNAL UC_BRAM_WEN_B_xhdl5      :  std_logic_vector(0 TO C_NUM_WE - 1);   
   SIGNAL UC_BRAM_Addr_B_xhdl6     :  std_logic_vector(0 TO C_PORT_AWIDTH - 1);   
   SIGNAL UC_BRAM_Dout_B_xhdl7     :  std_logic_vector(0 TO C_PORT_DWIDTH - 1);   

BEGIN
   UC_GPIO_Dout_A <= UC_GPIO_Dout_A_xhdl1;
   UC_BRAM_Rst_B <= UC_BRAM_Rst_B_xhdl2;
   UC_BRAM_Clk_B <= UC_BRAM_Clk_B_xhdl3;
   UC_BRAM_EN_B <= UC_BRAM_EN_B_xhdl4;
   UC_BRAM_WEN_B <= UC_BRAM_WEN_B_xhdl5;
   UC_BRAM_Addr_B <= UC_BRAM_Addr_B_xhdl6;
   UC_BRAM_Dout_B <= UC_BRAM_Dout_B_xhdl7;
   UC_BRAM_EN_B_xhdl4 <= '1' ;
   UC_BRAM_Clk_B_xhdl3 <= UC_Clk ;
   UC_BRAM_Rst_B_xhdl2 <= UC_Rst ;
   UC_BRAM_Dout_B_xhdl7 <= UC_GPIO_Din_A ;
   temp_xhdl8 <= "0100" WHEN bram_wr = '1' ELSE "0000";
   UC_BRAM_Addr_B_xhdl6 <= "0000000000000000000000000000" & temp_xhdl8 ;
   temp_xhdl9 <= "11111111111111111111111111111111" WHEN bram_wr = '1' ELSE "00000000000000000000000000000000";
   UC_BRAM_WEN_B_xhdl5 <= temp_xhdl9(3 DOWNTO 0) ;

   PROCESS (UC_Clk)
   BEGIN
      IF (UC_Clk'EVENT AND UC_Clk = '1') THEN
         IF (UC_Rst = '1') THEN
            bram_wr <= '0';    
         ELSE
            bram_wr <= NOT bram_wr;    
         END IF;
      END IF;
   END PROCESS;

   PROCESS (UC_Clk)
   BEGIN
      IF (UC_Clk'EVENT AND UC_Clk = '1') THEN
         IF (bram_wr = '1') THEN
            UC_GPIO_Dout_A_xhdl1 <= UC_BRAM_Din_B;    
         END IF;
      END IF;
   END PROCESS;

END ARCHITECTURE translated;