blkram_gpio.v

ULTRACTR的源码

//*****************************************************************************
//	Module: BlockRAM GPIO Interface
//*****************************************************************************
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//     
//     (c) Copyright 2002 Xilinx, Inc.
//     All rights reserved.
// 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename:     blkram_gpio.v
// 
// Description:    
// Module creates a 32 bit input and 32 bit latched output via a block ram interface
//	bram address 0 = data to be written to GPIO (read from BRAM)
//  bram address 4 = data read from GPIO (write to BRAM address)
//
// Design Notes:
// 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Author:  APD/SEG
// History: 2003.08.08 - initial release
// 
//
//-----------------------------------------------------------------------------

///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 ps

module uc_gpio_ref( UC_Rst, UC_Clk, UC_GPIO_Dout_A, UC_GPIO_Din_A,
	UC_BRAM_Rst_B, UC_BRAM_Clk_B, UC_BRAM_EN_B, UC_BRAM_WEN_B, 
	UC_BRAM_Addr_B, UC_BRAM_Din_B, UC_BRAM_Dout_B);

///////////////////////////////////////////////////////////////////////////////
// PARAMETER DECLARATION
///////////////////////////////////////////////////////////////////////////////

parameter C_FAMILY = "virtex2p";
parameter C_NUM_WE = 4;
parameter C_PORT_DWIDTH = 32;
parameter C_PORT_AWIDTH = 32;

///////////////////////////////////////////////////////////////////////////////
// port declarations
///////////////////////////////////////////////////////////////////////////////
	// external GPIO interface
	input UC_Rst;
	input UC_Clk;
	output [0:C_PORT_DWIDTH-1] UC_GPIO_Dout_A;
	input [0:C_PORT_DWIDTH-1] UC_GPIO_Din_A;
	// BRAM Port
	output UC_BRAM_Rst_B;
	output UC_BRAM_Clk_B;
	output UC_BRAM_EN_B;
	output [0:C_NUM_WE-1] UC_BRAM_WEN_B;
	output [0:C_PORT_AWIDTH-1] UC_BRAM_Addr_B;
	input  [0:C_PORT_DWIDTH-1] UC_BRAM_Din_B;
	output [0:C_PORT_DWIDTH-1] UC_BRAM_Dout_B;

///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
	reg bram_wr;	// set to high when writing to block ram and low when latching data for GPIO out
	reg [0:C_PORT_DWIDTH-1] UC_GPIO_Dout_A; // register data to be output from the GPIO

///////////////////////////////////////////////////////////////////////////////
// Signal Assignment
///////////////////////////////////////////////////////////////////////////////
	assign UC_BRAM_EN_B = 1;  // always enable the bram
	assign UC_BRAM_Clk_B = UC_Clk;  // clock the bram with the same clock as the GPIO interface
	assign UC_BRAM_Rst_B = UC_Rst;  // reset the bram with the GPIO reset
	assign UC_BRAM_Dout_B = UC_GPIO_Din_A; // always pass input data to the blockram
	// block ram address 4 for writes and 0 for reads
        assign UC_BRAM_Addr_B = bram_wr ? 4'b0100 : 4'b0000;
   	// set write enables equal to 1 when writing to RAM	
        assign UC_BRAM_WEN_B  = bram_wr ? (32'hFFFFFFFF) : 32'h0;


///////////////////////////////////////////////////////////////////////////////
// TOP LEVEL LOGIC
///////////////////////////////////////////////////////////////////////////////
	always @ (posedge UC_Clk)	// write and address on positive clock edge 
		if (UC_Rst) bram_wr <= 0;
		else bram_wr <= ~bram_wr; 	// toggle read/write state

	always @ (posedge UC_Clk)	// latch data read on positive edge
			if (bram_wr) UC_GPIO_Dout_A <= UC_BRAM_Din_B; 

 	endmodule