uc_gpio_ref_v2_1_0.mpd

ULTRACTR的源码

################################################################################
##
## Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
##
## UC_GPIO_ref_v1_0_0.mpd
## 
## Microprocessor Peripheral Definition -- UltraController GPIO Interface
##
################################################################################

BEGIN uc_gpio_ref
OPTION  IPTYPE=IP
OPTION  IMP_NETLIST=TRUE
OPTION  HDL=BOTH


OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL

# Bus interface definitions
BUS_INTERFACE BUS=GPIO_PORT, BUS_STD=TRANSPARENT, BUS_TYPE=UNDEF
BUS_INTERFACE BUS=BRAM_PORT, BUS_STD=TRANSPARENT, BUS_TYPE=UNDEF

# Generics for vhdl or parameters for verilog
PARAMETER C_NUM_WE = 4, DT=integer
PARAMETER C_PORT_DWIDTH = 32, DT=integer, BUS=BRAM_PORT
PARAMETER C_PORT_AWIDTH = 32, DT=integer, BUS=BRAM_PORT
PARAMETER C_FAMILY = virtex2p, DT=string


# GPIO Port
PORT UC_Rst = UC_Rst, DIR=IN, BUS=GPIO_PORT
PORT UC_Clk = UC_Clk, DIR=IN, BUS=GPIO_PORT, SIGIS=CLK
PORT UC_GPIO_Dout_A = UC_GPIO_Dout, DIR=OUT, VEC=[0:C_PORT_DWIDTH-1], BUS=GPIO_PORT
PORT UC_GPIO_Din_A = UC_GPIO_Din, DIR=IN, VEC=[0:C_PORT_DWIDTH-1], BUS=GPIO_PORT

# BRAM Port
PORT UC_BRAM_Rst_B = BRAM_Rst, DIR=OUT, BUS=BRAM_PORT
PORT UC_BRAM_Clk_B = BRAM_Clk, DIR=OUT, BUS=BRAM_PORT, SIGIS=CLK
PORT UC_BRAM_EN_B  = BRAM_EN,  DIR=OUT, BUS=BRAM_PORT
PORT UC_BRAM_WEN_B = BRAM_WEN, DIR=OUT, VEC=[0:C_NUM_WE-1], BUS=BRAM_PORT
PORT UC_BRAM_Addr_B =BRAM_Addr,DIR=OUT, VEC=[0:C_PORT_AWIDTH-1], BUS=BRAM_PORT
PORT UC_BRAM_Din_B = BRAM_Din, DIR=IN, VEC=[0:C_PORT_DWIDTH-1], BUS=BRAM_PORT
PORT UC_BRAM_Dout_B =BRAM_Dout,DIR=OUT, VEC=[0:C_PORT_DWIDTH-1], BUS=BRAM_PORT

END


# BRAM Port B