sequence.vhd

ULTRACTR的源码

end process;

-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
        if  ris_edge = '1' or Lpf_reset = '1' then
            pr <= '1';
        elsif pr_dec(2) = '1' then 
            pr <= '0';
      end if;
   end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use 
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
      if (seq_cnt(5 downto 3) = PR_END_CHIP(5 downto 3) and sys = '0')  or 
         (seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3)  and sys = '1')  then
         pr_dec(0) <= '1';          
      else
         pr_dec(0) <= '0';
      end if;
      if (seq_cnt(2 downto 0) = PR_END_CHIP(2 downto 0) and sys = '0') or
         (seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0)  and sys = '1') then
         pr_dec(1) <= '1';         
      else
         pr_dec(1) <= '0';
      end if;
      pr_dec(2) <= pr_dec(1) and pr_dec(0); 
   end if;
end process;

-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
CHIP_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
        if ris_edge = '1' or Lpf_reset = '1' then
            chip <= '1';
        elsif chip_dec(2) = '1' then
            chip <= '0';
      end if;
   end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for Chip to use 
-------------------------------------------------------------------------------
CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
begin
   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
      if (seq_cnt(5 downto 2) = CHIP_END(5 downto 2))  then 
         chip_dec(0) <= '1';          
      else
         chip_dec(0) <= '0';
      end if;
      if (seq_cnt(1 downto 0) = CHIP_END(1 downto 0)) then
         chip_dec(1) <= '1';         
      else
         chip_dec(1) <= '0';
      end if;
      chip_dec(2) <= chip_dec(1) and chip_dec(0); 
   end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
SYS_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
        if sys_edge = '1' or Lpf_reset = '1' then
            sys <= '1';
        elsif sys_dec(2) = '1' then
            sys <= '0';
      end if;
   end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for Sys to use 
-------------------------------------------------------------------------------
SYS_DECODE_PROCESS: process (Slowest_sync_clk)
begin
   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
      if (seq_cnt(5 downto 2) = SYS_END(5 downto 2))  then 
         sys_dec(0) <= '1';          
      else
         sys_dec(0) <= '0';
      end if;
      if (seq_cnt(1 downto 0) = SYS_END(1 downto 0)) then
         sys_dec(1) <= '1';         
      else
         sys_dec(1) <= '0';
      end if;
      sys_dec(2) <= sys_dec(1) and sys_dec(0); 
   end if;
end process;

-------------------------------------------------------------------------------
-- This process delays signals so the the edge can be detected and used 
-------------------------------------------------------------------------------
DELAY_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         chip_reset_req_d1   <= Chip_Reset_Req  ;
         chip_reset_req_d2   <= chip_Reset_Req_d1  ;
         chip_reset_req_d3   <= chip_Reset_Req_d2  ;
         system_reset_req_d1 <= System_Reset_Req;
         system_reset_req_d2 <= system_Reset_Req_d1;
         system_reset_req_d3 <= system_Reset_Req_d2;
      end if;
   end process;

-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
RIS_EDGE_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         if   (chip_reset_req_d3='0'   and chip_Reset_Req_d2= '1') -- rising edge  
           or (system_reset_req_d3='0' and system_Reset_Req_d2='1')-- rising edge
         then 
            ris_edge <= '1';
         else
            ris_edge <='0';
         end if;
      end if;
   end process;
   
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of 
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_EDGE_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         if   (system_reset_req_d3='0' and system_reset_req_d2='1')-- rising edge  
         then 
            sys_edge <= '1';
         else
            sys_edge <='0';
         end if;
      end if;
   end process;
   
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing 
-------------------------------------------------------------------------------
   SEQ_COUNTER : UPCNT_N
   generic map (
                C_SIZE => 6 
               )
      
     port map( 
              Data     => "000000",
              Cnt_en   => seq_cnt_en,
              Load     => '0',
              Clr      => seq_clr,  
              Clk      => Slowest_sync_clk, 
              Qout     => seq_cnt 
             );

-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
--  This generates the reset pulse and the count enable to core reset counter
--  count until are outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
   begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         if (Lpf_reset='1' or System_Reset_Req_d3='1' or Chip_Reset_Req_d3='1'
                           or ris_edge = '1')
            then seq_cnt_en <= '1';
         elsif  Bsr='0' and Pr='0' and 
                Chip='0' and Sys='0'
            then seq_cnt_en <= '0';
         end if;
      end if;
   end process;

-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
--  This generates the reset to the sequence counter
--  Clear the counter on a rising edge of chip or system request or low pass
--  filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
   begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         if  ris_edge = '1' or Lpf_reset = '1' then
            seq_clr <= '0';
         else
            seq_clr <= '1';
         end if;
      end if;
   end process;
end imp;