sequence.vhd

ULTRACTR的源码

-------------------------------------------------------------------------------
-- $Id: sequence.vhd,v 1.4 2003/05/16 16:26:39 conover Exp $
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        sequence.vhd
--
-- Description:     
--                  This file control the sequencing coming out of a reset.
--                  The sequencing is as follows:
--                  Bus_Struct_Reset comes out of reset first.  Either when the
--                     external or auxiliary reset goes inactive or 16 clocks 
--                     after a 405 Chip_Reset_Request, or 30 clocks after a 405
--                     System_Reset_Request.
--                  Peripheral_Reset comes out of reset 16 clocks after 
--                     Bus_Struct_Reset.
--                  The 405 resetcore, resetchip, resetsystem come out of reset
--                     16 clocks after Peripheral_Reset.
--
-------------------------------------------------------------------------------
-- Structure:   
--
--              sequence.vhd
--
-------------------------------------------------------------------------------
-- Author:      Kurt Conover
-- History:
--  Kurt Conover      11/12/01      -- First Release
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
--          Lpf_reset            -- Low Pass Filtered in 
--          System_Reset_Req     -- System Reset Request
--          Chip_Reset_Req       -- Chip Reset Request
--          Slowest_Sync_Clk     -- Clock                
--          Bsr_out              -- Bus Structure Reset out 
--          Pr_out               -- Peripheral Reset out
--          Core_out             -- Core reset out
--          Chip_out             -- Chip reset out
--          Sys_out              -- System reset out
--
-------------------------------------------------------------------------------
entity sequence is
	port(
        Lpf_reset                : in  std_logic;                          
	     System_Reset_Req         : in  std_logic; 
	     Chip_Reset_Req           : in  std_logic;                           
	     Slowest_Sync_Clk         : in  std_logic;   
 	     Bsr_out                  : out std_logic;                          
        Pr_out                   : out std_logic; 
        Core_out                 : out std_logic; 
        Chip_out                 : out std_logic; 
        Sys_out                  : out std_logic  
	    );
		
end sequence;

architecture imp of sequence is

constant CLEAR : std_logic := '0';
constant BSR_END_CHIP : std_logic_vector(5 downto 0) := "001100";
constant BSR_END_SYS  : std_logic_vector(5 downto 0) := "011001";
constant PR_END_CHIP  : std_logic_vector(5 downto 0) := "011100";
constant PR_END_SYS   : std_logic_vector(5 downto 0) := "101001";
constant CHIP_END     : std_logic_vector(5 downto 0) := "101100";
constant SYS_END      : std_logic_vector(5 downto 0) := "111001";

signal bsr                 : std_logic := '0';
signal bsr_dec             : std_logic_vector(2 downto 0) := (others => '0');
signal pr                  : std_logic := '0';
signal pr_dec              : std_logic_vector(2 downto 0) := (others => '0');
signal Core                : std_logic := '0'; 
signal Chip                : std_logic := '0';
signal chip_dec            : std_logic_vector(2 downto 0) := (others => '0');
signal Sys                 : std_logic := '0';
signal sys_dec             : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1   : std_logic := '0';  -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2   : std_logic := '0';  -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3   : std_logic := '0';  -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0';  -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0';  -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0';  -- delayed System_Reset_Req
signal seq_cnt             : std_logic_vector(5 downto 0);
signal seq_cnt_en          : std_logic := '0';
signal seq_clr             : std_logic := '0';

signal ris_edge            : std_logic := '0'; 
signal sys_edge            : std_logic := '0'; 


-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Up counter - C-SIZE bits
component UPCNT_N
   generic (
            C_SIZE : Integer 
           );
   port(
        Data   : in std_logic_vector (C_SIZE-1 downto 0);  
        Cnt_en : in std_logic;                             
        Load   : in std_logic;                             
        Clr    : in std_logic;                             
        Clk    : in std_logic;                             
        Qout   : out std_logic_vector (C_SIZE-1 downto 0)
       );
end component; 


begin

   Pr_out  <= pr;
   Bsr_out <= bsr;
   Core_out <= sys or chip;
   Chip_out <= sys or chip;
   Sys_out  <= sys;

-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
        if ris_edge = '1' or Lpf_reset = '1' then
            bsr <= '1';
        elsif bsr_dec(2) = '1' then
            bsr <= '0';
      end if;
   end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
   if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
      if (seq_cnt(5 downto 3) = BSR_END_CHIP(5 downto 3) and sys = '0')  or 
         (seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and sys = '1') then
         bsr_dec(0) <= '1';         
      else
         bsr_dec(0) <= '0';
      end if;
      if (seq_cnt(2 downto 0) = BSR_END_CHIP(2 downto 0) and sys = '0') or
         (seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and sys = '1') then
         bsr_dec(1) <= '1';         
      else
         bsr_dec(1) <= '0';
      end if;
      bsr_dec(2) <= bsr_dec(1) and bsr_dec(0); 
  end if;