proc_sys_reset.vhd

ULTRACTR的源码

-- Component Declarations
-------------------------------------------------------------------------------
-- Up counter - C-SIZE bits
component UPCNT_N
   generic (
            C_SIZE : Integer 
           );
   port(
        Data   : in std_logic_vector (C_SIZE-1 downto 0);  -- Serial data in
        Cnt_en : in std_logic;                             -- Count enable
        Load   : in std_logic;                             -- Load line enable
        Clr    : in std_logic;                             -- Active low clear
        Clk    : in std_logic;                             -- Clock
        Qout   : out std_logic_vector (C_SIZE-1 downto 0)
       );
end component; 

-- Low Pass Filter and meta-stability
component LPF
   generic (
            C_EXT_RST_WIDTH    : Integer;
            C_AUX_RST_WIDTH    : Integer; 
            C_EXT_RESET_HIGH   : std_logic;
            C_AUX_RESET_HIGH   : std_logic
          );
   port(
        Dcm_locked               : in  std_logic;
        External_System_Reset    : in  std_logic; -- External Reset Input
        Auxiliary_System_Reset   : in  std_logic; -- Auxiliary reset input                          
        Slowest_Sync_Clk         : in  std_logic; -- Clock                  
        Lpf_reset                : out std_logic  -- Low Pass Filtered out                          
       );
end component;

-- Sequencer for coming out of reset
component SEQUENCE

   port(
        Lpf_reset                : in  std_logic; -- Low Pass Filtered in                          
        System_Reset_Req         : in  std_logic; -- External Reset Input
        Chip_Reset_Req           : in  std_logic; -- Auxiliary reset input                          
        Slowest_Sync_Clk         : in  std_logic; -- Clock                  
        Bsr_out                  : out std_logic; -- Bus_Struct_Reset out                          
        Pr_out                   : out std_logic; -- Peripheral_Reset
        Core_out                 : out std_logic; -- Core reset
        Chip_out                 : out std_logic; -- Chip reset
        Sys_out                  : out std_logic  -- System reset
       );
end component;  
   
            
begin
-------------------------------------------------------------------------------
-- This process defines the Rstc405reset outputs 
-------------------------------------------------------------------------------
Rstc_output_PROCESS: process (Slowest_sync_clk)
   begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         Rstc405resetcore  <= not (core_cnt(3) and core_cnt(2) and core_cnt(1)
                                   and core_cnt(0)) 
                                   or Core_out;
                                   
                                   
         Rstc405resetchip  <= Chip_out; 
                                   
         Rstc405resetsys   <= Sys_out;  
          
      end if;
   end process;

-------------------------------------------------------------------------------
-- This process delays signals so the the edge can be detected and used 
--  Double register to sync up with slowest_sync_clk
-------------------------------------------------------------------------------
DELAY_PROCESS: process (Slowest_sync_clk)
begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         core_reset_req_d1   <= Core_Reset_Req  ;
         core_reset_req_d2   <= core_reset_req_d1;
         core_reset_req_d3   <= core_reset_req_d2;
      end if;
   end process;

-------------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-------------------------------------------------------------------------------
      BSR_OUT_DFF: for i in 0 to C_NUM_BUS_RST - 1 generate
         BSR_DFF : process (Slowest_Sync_Clk)
         begin
            if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
               Bus_Struct_Reset(i) <= Bsr_out;
            end if;
         end process;
      end generate BSR_OUT_DFF;

-------------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-------------------------------------------------------------------------------
      PR_OUT_DFF: for i in 0 to C_NUM_PERP_RST - 1 generate
         PR_DFF : process (Slowest_Sync_Clk)
         begin
            if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
               Peripheral_Reset(i) <= Pr_out;
            end if;
         end process;
      end generate PR_OUT_DFF;


-------------------------------------------------------------------------------
-- This instantiates a counter to ensure the Core_Reset_Req will genereate a 
-- Rstc045resetcore that is a mimimum of 15 clocks
-------------------------------------------------------------------------------
   CORE_RESET : UPCNT_N
   generic map (
                C_SIZE => 4 
               )
      
     port map( 
              Data     => "0000",
              Cnt_en   => core_cnt_en,
              Load     => '0',
              Clr      => core_req_edge,  
              Clk      => Slowest_sync_clk, 
              Qout     => core_cnt 
             );
      
-------------------------------------------------------------------------------
-- CORE_RESET_PROCESS
-------------------------------------------------------------------------------
--  This generates the reset pulse and the count enable to core reset counter
--
CORE_RESET_PROCESS: process (Slowest_sync_clk)
   begin
      if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
         core_cnt_en <= not (core_cnt(3) and core_cnt(2) and core_cnt(1))
                        or not core_req_edge;
         core_req_edge <= not(core_Reset_Req_d2 and not core_reset_req_d3);         
      end if;
   end process;

-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary 
-- Reset Inputs.
-------------------------------------------------------------------------------
   EXT_LPF : LPF
   generic map (
           C_EXT_RST_WIDTH    => C_EXT_RST_WIDTH   ,  
           C_AUX_RST_WIDTH    => C_AUX_RST_WIDTH   ,  
           C_EXT_RESET_HIGH   => C_EXT_RESET_HIGH  , 
           C_AUX_RESET_HIGH   => C_AUX_RESET_HIGH 
              )
   port map(
            Dcm_locked               => Dcm_locked        ,
            External_System_Reset    => Ext_Reset_In      , 
            Auxiliary_System_Reset   => Aux_Reset_In      ,
            Slowest_Sync_Clk         => Slowest_Sync_Clk  ,
            Lpf_reset                => Lpf_reset             
           );
           
-------------------------------------------------------------------------------
-- This instantiates the sequencer  
--  This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
   SEQ : SEQUENCE
   port map(
            Lpf_reset              => Lpf_reset         , 
            System_Reset_Req       => System_Reset_Req  ,
            Chip_Reset_Req         => Chip_Reset_Req    ,
            Slowest_Sync_Clk       => Slowest_Sync_Clk  ,  
            Bsr_out                => Bsr_out           ,
            Pr_out                 => Pr_out            ,
            Core_out               => Core_out          ,
            Chip_out               => Chip_out          ,
            Sys_out                => Sys_out  
           );           
           
end imp;

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