proc_sys_reset.vhd

ULTRACTR的源码

--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: proc_sys_reset.vhd,v 1.4 2003/05/16 16:26:39 conover Exp $
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
--  **                                                                       **
--  **  This text contains proprietary, confidential                         **
--  **  information of Xilinx, Inc. , is distributed by                      **
--  **  under license from Xilinx, Inc., and may be used,                    **
--  **  copied and/or disclosed only pursuant to the terms                   **
--  **  of a valid license agreement with Xilinx, Inc.                       **
--  **                                                                       **
--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
--  **  specification. Source code is provided "as-is", with no              **
--  **  obligation on the part of Xilinx to provide support.                 **
--  **                                                                       **
--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
--  **  version of the core (and thus indirectly, the original core source). **
--  **                                                                       **
--  **  The Xilinx Support Hotline does not have access to source            **
--  **  code and therefore cannot answer specific questions related          **
--  **  to source HDL. The Xilinx Support Hotline will only be able          **
--  **  to confirm the problem in the Netlist version of the core.           **
--  **                                                                       **
--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        proc_sys_reset.vhd
-- 
-- Description:     Parameterizeable top level processor reset module.
--                  
--
-------------------------------------------------------------------------------
-- Structure:   This section should show the hierarchical structure of the 
--              designs. Separate lines with blank lines if necessary to improve
--              readability.
--
--              proc_sys_reset.vhd
--                  -- upcnt_n.vhd
--                      -- third_level_file1.vhd
--                          -- fourth_level_file.vhd
--                      -- third_level_file2.vhd
--                  -- second_level_file2.vhd
--                  -- second_level_file3.vhd
--
--              This section is optional for common/shared modules but should
--              contain a statement stating it is a common/shared module.
-------------------------------------------------------------------------------
-- Author:      kc
-- History:
--  kc           11/07/01      -- First version
--
--  kc           02/25/2002    -- Changed generic names C_EXT_RST_ACTIVE to
--                                C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
--                                C_AUX_RESET_HIGH to match generics used in
--                                MicroBlaze.  Added the DCM Lock as an input
--                                to keep reset active until after the Lock
--                                is valid.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_cmb" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--          C_EXT_RST_WIDTH       -- External Reset Low Pass Filter setting
--          C_AUX_RST_WIDTH       -- Auxiliary Reset Low Pass Filter setting   
--          C_EXT_RESET_HIGH      -- External Reset Active High or Active Low
--          C_AUX_RESET_HIGH      -= Auxiliary Reset Active High or Active Low
--          C_NUM_BUS_RST         -- Number of Bus Structures reset to generate
--          C_NUM_PERP_RST        -- Number of Peripheral resets to generate
--
--
-- Definition of Ports:
--          Slowest_sync_clk       -- Clock 
--          Ext_Reset_In           -- External Reset Input
--          Aux_Reset_In           -- Auxiliary Reset Input
--          Core_Reset_Req         -- PPC Core reset request                
--          Chip_Reset_Req         -- PPC Chip reset request 
--          System_Reset_Req       -- PPC System reset request
--          Dcm_locked             -- DCM Locked, hold system in reset until 1
--          Rstc405resetcore       -- PPC core reset out
--          Rstc405resetchip       -- PPC chip reset out
--          Rstc405resetsys        -- PPC system reset out
--          Bus_Struct_Reset       -- Bus structure reset out
--          Peripheral_Reset       -- Peripheral reset out
--
-------------------------------------------------------------------------------
entity proc_sys_reset is
    generic (
              C_EXT_RST_WIDTH          : integer   := 4;
              C_AUX_RST_WIDTH          : integer   := 4;
              C_EXT_RESET_HIGH         : std_logic := '1'; -- High active input
              C_AUX_RESET_HIGH         : std_logic := '1'; -- High active input
              C_NUM_BUS_RST            : integer   := 1;
              C_NUM_PERP_RST           : integer   := 1
            );
            
    port (
          Slowest_sync_clk     : in  std_logic;
          Ext_Reset_In         : in  std_logic;
          Aux_Reset_In         : in  std_logic;
          Core_Reset_Req       : in  std_logic;
          Chip_Reset_Req       : in  std_logic;
          System_Reset_Req     : in  std_logic;
          Dcm_locked           : in  std_logic := '1';
          Rstc405resetcore     : out std_logic := '0';
          Rstc405resetchip     : out std_logic := '0';
          Rstc405resetsys      : out std_logic := '0';
          Bus_Struct_Reset     : out std_logic_vector(0 to C_NUM_BUS_RST - 1) 
                                      := (others => '0');
          Peripheral_Reset     : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
                                      := (others => '0')
         );
            
end entity proc_sys_reset;

-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is

-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------

constant ALL_ONES   : std_logic_vector(7 downto 0)  := "11111111";
constant DE         : std_logic_vector(7 downto 0)  := "11011110";
constant AD         : std_logic_vector(7 downto 0)  := "10101101";
constant BE         : std_logic_vector(7 downto 0)  := "10111110";
constant EF         : std_logic_vector(7 downto 0)  := "11101111";

-------------------------------------------------------------------------------
-- Signal and Type Declarations
signal Core_Reset_Req_d1   : std_logic := '0';  -- delayed Core_Reset_Req
signal Core_Reset_Req_d2   : std_logic := '0';  -- delayed Core_Reset_Req
signal Core_Reset_Req_d3   : std_logic := '0';  -- delayed Core_Reset_Req

signal core_cnt_en         : std_logic := '0'; -- Core_Reset_Req counter enable

signal core_req_edge       : std_logic := '1'; -- Rising edge of Core_Reset_Req

signal core_cnt     : std_logic_vector(3 downto 0); -- core counter output

signal lpf_reset    : std_logic; -- Low pass filtered ext or aux

signal Bsr_out      : std_logic;
signal Pr_out       : std_logic;
signal Core_out     : std_logic;
signal Chip_out     : std_logic;
signal Sys_out      : std_logic;
-------------------------------------------------------------------------------