proc_sys_reset_v2_0_0.mpd

ULTRACTR的源码

################################################################################
##
## Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
##
## proc_sys_reset_v2_0_0.mpd
##
## Microprocessor Peripheral Definition file
##
################################################################################

BEGIN proc_sys_reset, IPTYPE=IP, EDIF=TRUE

OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL

# Generics for vhdl or parameters for verilog
PARAMETER C_EXT_RST_WIDTH   = 4	, DT=integer  
PARAMETER C_AUX_RST_WIDTH   = 4	, DT=integer  
PARAMETER C_EXT_RESET_HIGH  = 1	, DT=std_logic
PARAMETER C_AUX_RESET_HIGH  = 1	, DT=std_logic
PARAMETER C_NUM_BUS_RST     = 1	, DT=integer  
PARAMETER C_NUM_PERP_RST    = 1	, DT=integer  

# proc_sys_reset signals
PORT Slowest_sync_clk   = "", DIR=IN, SIGIS=CLK
PORT Ext_Reset_In       = "", DIR=IN
PORT Aux_Reset_In       = "", DIR=IN
PORT Core_Reset_Req     = "", DIR=IN
PORT Chip_Reset_Req     = "", DIR=IN
PORT System_Reset_Req   = "", DIR=IN
PORT Dcm_locked         = "", DIR=IN
PORT Rstc405resetcore   = "", DIR=OUT
PORT Rstc405resetchip   = "", DIR=OUT
PORT Rstc405resetsys    = "", DIR=OUT
PORT Bus_Struct_Reset   = "", DIR=OUT, VEC=[0:C_NUM_BUS_RST-1]
PORT Peripheral_Reset   = "", DIR=OUT, VEC=[0:C_NUM_PERP_RST-1]

END